Henderson, NV – May 24, 2016 – Aldec, Inc. a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, once again delivers free technical sessions the Design Automation Conference (DAC), June 5-9, 2016, in Austin, Texas.
Technical Sessions and Demos
Daily (June 6-8, 2016) at Booth #619
Spots fill up quickly. Register to reserve your free, in-depth technical session.
01: Adopting Accellera SCE-MI standard to reuse FPGA Boards for Simulation Acceleration and Co-emulation
02: Solutions for High Performance Computing (HPC) on FPGA
03: Aldec ASIC Verification Spectrum: A scalable solution from block-level to system-level
04: Design Prototyping on a Scaleable Platform Built on Xilinx Ultrascale FPGA Technology
05: Best Practices for Managing Functional Specification
06: Efficient CDC Debugging Using Phase-based Methodology for Large FPGA/ASIC Multi-clock Designs
07: At-Speed FPGA Testing, Testbench Reuse and Dynamic Functional Equivalency Checking with RTL Simulation
08: Functional Verification: The Good, the Bad, the Ugly
09: High Level Synthesis with NEC
10: IoT Applications on TySOM Development Board
View complete Abstracts and Registration at www.aldec.com/dac2016.
The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. Close to 300 technical presentations and sessions are selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies.
A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging companies in:
The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design Automation (SIGDA). www.dac.com
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.
|Media Contact:||Aldec, Inc.
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400