Q4-2012 - Aldec™ Design and Verification Newsletter

Date: 2012/10/24Type: Newsletter

Technical Articles

Improve Productivity with User-Defined Design Management
Automatically Perform Repetitive Tasks with Mouse Strokes
Mitigating Metastability Issues in Asynchronous Designs
When to Consider Aldec Cloud™ for Batch Simulations
Reusing Testbench for RTL Validation in the C-based LSI Design Flow
DO-254: Increasing Verification Coverage by Test


UVM Webinar for Hardware Designers, "Don't Be Afraid of UVM"
Aldec Enters ASIC Prototyping Market with the HES-7
ASIC/SoC Prototyping with Aldec's New HES-7 Board
Product Updates


Corporate Standardization of FPGA Design Flow
Aldec's YouTube Videos: Unlock The Powerful Waveform Viewer

Improve Productivity with User-Defined Design Management

Project Task ManagementWorking with today's complex FPGA projects involves dealing with many different types of HDL files, IPs, libraries, schematics, waveforms etc. Every engineer must juggle these files many times during the FPGA design development phase, and it is critical that FPGA design tools allow users to define and organize the structure of the FPGA project based on user needs. Read More


Automatically Perform Repetitive Tasks with Mouse Strokes


Mice. These ubiquitous yet powerful devices can increase user productivity when used efficiently. Mouse Strokes allow users to perform common and repetitive tasks with simple mouse movements. This is especially convenient when using today’s popular dual or multiple screens that require a fair amount of mouse movement - particularly when using tools menus. Read More

UVM Webinar for Hardware Designers, "Don't Be Afraid of UVM"DontScaredUVMWebinar

This unintimidating webinar will begin with a solid review of SystemVerilog interfaces with special attention paid to those mysterious Virtual Interfaces, proceeding to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is also explained. Read More

Aldec Enters ASIC Prototyping Market with the HES-7


Aldec recently released HES-7™, a scalable prototyping board that allows designers the ability to verify ASIC/SoC designs up to 24 million gates. HES-7 utilizes new Xilinx® Virtex®-7 FPGAs which implement Stacked Silicon Read More

Webinar: ASIC/SoC Prototyping with Aldec's New HES-7 Board

Aldec's newly released FPGA-based prototyping platform, HES-7™, leverages Xilinx® Virtex®-7 FPGA. Read More

Mitigating Metastability Issues in Asynchronous Designs

The system reset carries out a critical function of forcing the SoC into a predictable state. Depending on what's appropriate for SoC's target application, the designer may use the Asynchronous or Synchronous reset method, or even a combination of the two.

Read More

DO-254: Increasing Verification Coverage by Test

As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified and alternative means of verification provided. Certification authorities favor verification by test for formal verification because of the simple fact that hardware flies, not simulation models. Requirements describing FPGA pin level behavior must be verified by test. Read More

When to Consider Aldec Cloud™ for Batch SimulationsAldec_Cloud

As cloud based services become more popular and efficient, it raises the question: Is cloud the right way to go for me? The answer depends on what you are planning to achieve by using the cloud. Read More

Reusing Testbench for RTL Validation in the C-based LSI Design Flow

Tools like Xilinx® Vivado™ HLS and NEC CyberWorkBench enable an alternative approach to the traditional IC design methodology by providing algorithmic (rather than typical hardware) development environment. Instead of manually creating a register-transfer-level (RTL) implementation, designers can cut development time by orders of magnitude by representing their algorithms at a higher level of abstraction (C, C++, or SystemC) and verifying reference system behavior at the same level of abstraction. Read More

Corporate Standardization of FPGA Design Flow

Today's FPGA designer is faced with many design challenges created from the increased time to market demands and complexities of their design. With the added external demands stemming from employee turnover and the proprietary nature of designs, Active-HDL offers the needed flexibility for organizations confronted with the development of programmable logic designs. Read More

Aldec's YouTube Videos: Unlock The Powerful Waveform ViewerAldec YouTube Channel

The Waveform Viewer window is an essential debugging tool that allows you to view the results of your simulation as timing waveforms. The Viewer allows you to see the signal transitions over time and relation of those signals with other signals in a design, zoom in and out over a time sequence, take measurements between Read More

Product Updates

Active-HDL™ 9.2

The latest release of Active-HDL introduces advanced features to boost productivity. Active-HDL 9.2 introduces the powerful concept of Flexible File Management to simplify FPGA project management by allowing customization and the ability to create common project structure across multiple vendor tools.

Major features that are included in Active-HDL 9.2 are:

User-defined Design Management - Customize directory structure to fit project environment. No need to use directory structure across multiple vendor tools.

Mouse Strokes – Perform common tasks with simple mouse movements.

Multiple symbols for same library unit - Generate multiple variances of a symbol for the same VHDL entity or Verilog module. Create different shape and color symbols for the same library unit.

Route optimization for schematics - Automatically optimize and reduce redundant net segment on schematics.

Annotate Waveform - Place message balloons on waveform for enhanced debugging and documentation.

Support for latest FPGA device - Design flow manager updated to support latest vendor tools and libraries.

New Features and Enhancements: Active-HDL 9.2 Release Notes

What's New Presentation: What's New in Active-HDL 9.2


Riviera-PRO™ 2012.10 available for download November 5, 2012

Riviera-PRO™ 2012.10 delivers numerous stability and performance improvements, new language constructs, and the latest versions of industry-standard verification libraries.

Key changes, updates, and new features include:

New SV constructs ('foreach' and dynamic array size randomization), SVA seq.triggered

Universal Verification Methodology (UVM) library version 1.1c

VHDL 2008 local packages and simulation performance (up to 15% on select designs)

Upgrade to the latest SystemC library version 2.3.0 (IEEE 1666™-2011 Standard)

Improved MATLAB interface (passing structures, and new use scenario / MATLAB as a master)

Enhanced waveform (incremental find, virtual arrays in analog view, simulation messages)

150+ customer requests and issues


ALINT 2012.12™ coming December 2012

ALINT™ design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage.

New Features to look forward to include:

New rules in ALDEC_VLOG and ALDEC_VHDL rule plug-ins to help reduce long routing delays. New rules address issues associated with fanout, logic levels, and output registers.

Tighter integration with Riviera-PRO verification platform. Project teams that develop with Aldec tools will be able to take automated code reviews to the next level by quickly creating project tasks based on violations detected during a linting session. Team members performing code reviews or audits will be able to quickly create and delegate action items to the others.

Instant code analysis in HDL Editor. Instant analysis will be automatically performed while code is being edited. (If new code contains errors, an error marker is displayed on the HDL Editor margin).



HES-DVM™ is a complete ASIC/SoC hardware-based verification solution that provides a unified platform for bit level simulation acceleration, transaction level emulation, system architecture exploration, HW/SW co-verification, virtual modeling and ASIC prototyping.

New Features and updates:

SCE-MI 2.0 Compiler Now Supports:
- Shared registers are converted from multi-source assignments into merged logic that is synthesizable allowing for easier coding of transactors.
- Implicit State Machines for easier coding of SCE-MI transactors, no need to maintain explicit state registers and is faster to adopt by Verification Engineers.
- Messages Streaming is optimized for speed to improve co-emulation runtime speeds. It supports a non-blocking message transport and data streams that do not require delivery confirmation.

Easy Hardware Clock Connection for Speed-Bridge with complete integration from within the emulation setup mode. Connects at any hierarchy level and automatically generates implementation constraints for hardware clocks.

4x speed improvement in SystemC co-simulation over previous release. Added static debug probes for support of bits and vectors.



Aldec recently unveiled HES-7™, a scalable, high quality FPGA-based ASIC prototyping solution for SoC/ASIC hardware verification and software validation teams backed by an industry leading 1-Year warranty.

Top Features and Benefits of HES-7 include:

Scalable Capacity Each HES-7 board with dual Xilinx® Virtex®-7 2000T has 4 million FPGA logic cells or up to 24 million ASIC gates of capacity, not including the DSP and memory resources.

Easy To Use with Reduced Design Partitioning Architected to allow for easy implementation and expansion using only one or two large FPGAs, rather than multiple low density FPGAs, HES-7 does not require as much labor-intensive partitioning or tool expense.

Expandable via Non-Proprietary Connector Using a non-proprietary HES-7 backplane connector, HES-7 can easily expand prototype capacity up to 96 million ASIC gates and can include the expansion of daughter boards.

Lowers ASIC Prototyping Cost By keeping costs lower through operational efficiencies, high volume manufacturing, and a close partnership with Xilinx who brings superior design implementation and debug software to the process at affordable prices, Aldec is able to pass savings on to customers.



  • Advanced Verification Platform (OVM/UVM, VMM)
  • IEEE Std. Compliant High-Performance Simulator
  • Assertion-Based Verification (SVA, PSL, OVA)
  • Code and Functional Coverage
  • Powerful IDE, Tcl scripting
  • Co-Simulation with DSP and RF Tools
  • Linux and Windows 32/64-Bit


  • FPGA Design & Verification
  • Graphical Design Entry
  • Mixed-Language Simulator
  • Code Coverage Tools
  • MATLAB®/Simulink® Interface
  • HTML & PDF Documentation 


  • Early bugs detection (RTL)
  • Industry-proven design guidelines
  • Guided design refinement (PBL)
  • In-house design expertise automation
  • IDE for in-depth design troubleshooting
  • VHDL, Verilog®, mixed-language
  • C++ based API (custom rules


  • 10MHz Emulation Speed
  • SCE-MI 2.0 DPI-C Support
  • Integration with Riviera-PRO: Adding/Removing Debugging Signals and Emulation Start/Stop/Step
  • Speed improvements for SystemC co-simulation
  • Hardware clock connection for speed bridges


  • Scalable Capacity From 4 - 96 million ASIC Gates
  • Easy To Use with Reduced Design Partitioning
  • Expandable via Non-Proprietary Connector
  • Superior Quality Backed by Industry Leading 1-Year Warranty
  • Lowers Cost of Overall ASIC Prototype Process

Did You Know?

In Riviera-PRO, once at a breakpoint, you may need to expand a hierarchical data structure out to see the values of particular data members in the Locals window. It may take many clicks if the structure is complex (typical for verification environments using SystemVerilog and UVM). At the next step to a breakpoint, the Locals window resets from the expanded display forcing you to start over. To prevent this, use Preferences | Debug | General | Do not collapse dynamic objects while stepping. This option is disabled by default to ensure the optimal GUI performance.

While generating a code coverage report, it is common to exclude the testbench related information. The 'asim' commands features a dedicated -cc_exclude switch that enables you to exclude a certain design region or file from the coverage report. See related FAQ.

Active-HDL allows users to stamp text message on accelerated waveform viewer to trace the flow of test or to find injected stimulus.

Accelerated waveform viewer files can be exported to graphics (*.bmp, *.jpeg, *.png) for easy sharing between users.



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