SOC Central: Verific Design Automation's SystemVerilog, VHDL Parsers Linked with Aldec's Hardware Emulation Solution

Date: 2012/08/15Type: In the News

SOC Central: Verific Design Automation's SystemVerilog, VHDL Parsers Linked with Aldec's Hardware Emulation Solution



Printed version of site: www.aldec.com/jp/company/news/2012-08-15