EE Times: Automatic C-to-VHDL Testbench Generation Shortens FPGA Development Time
Date: 2012/04/11Type: In the News
Printed version of site: www.aldec.com/jp/company/news/2012-04-11/119/print_page/www.aldec.com/jp/company/news/2012-04-11/www.aldec.com/jp/company/news/2012-04-11/119/print_page/www.aldec.com/jp/compa