Henderson, NV – November 14, 2011 Aldec, Inc. today released Riviera-PRO™ 2011.10 with complete support for the UVM (Universal Verification Methodology), Version 1.1. The latest release enhances the SystemVerilog verification methodology by providing extended language construct support and adding debugging and productivity features in the waveform. The new language construct enhancements, based on an industry accepted IEEE 1800™-2009 standard, enable customers to do extensive debugging and provide a path to support for UVM together with previous OVM (Open Verification Methodology) and alternative VMM (Verification Methodology Manual) methodologies.
“There are two major open source verification methodologies today, UVM/OVM and VMM – complete standalone solutions that approach the structure of verification environment in different ways,” said Dmitry Melnik, Riviera-PRO Product Manager. “Over the last few years end-users were choosing one of the methodologies to create their verification environments. As a result, a significant amount of legacy code and existing VIP (Verification Intellectual Property) are turning into the challenges of migrating to the alternative library or integrating with VIP from the other methodology.”
With the release of Riviera-PRO 2011.10, Aldec supports the latest version of UVM and related extensions:
UVM 1.1 is immediately available with Riviera-PRO 2011.10 installation today.
For additional information about Riviera-PRO 2011.10 including tutorials, downloads, and a “What’s New” presentation, visit www.aldec.com/products/riviera-pro.
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. More information about the company and its products is available at www.aldec.com.
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|Media Contact:||Christina Toole, Aldec, Inc.