dac 2016

asic verification spectrum

Aldec Verification Tools Implement the ASIC Verification Flow
Insights from Dr. Stanley Hyduke, Aldec Founder and CEO

Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability of FPGAs have increased, however, the distinction between FPGA and ASIC design has narrowed...

Design Automation Conference (DAC 2016)
June 6-8, 2016 | Austin, Texas
Booth #619
Register to learn more at an Aldec presentation at DAC.
01: Adopting SCE-MI standard to reuse FPGA Boards for Simulation Acceleration and Co-emulation
02: Solutions for High Performance Computing (HPC) on FPGA
03: Aldec ASIC Verification Spectrum: A scalable solution from block-level to system-level
04: Design Prototyping on a Scaleable Platform Built on Xilinx Ultrascale FPGA Technology
05: Best Practices for Managing Functional Specification
06: Efficient CDC Debugging Using Phase-based Methodology for Large FPGA/ASIC Multi-clock Designs
07: At-Speed FPGA Testing, Testbench Reuse and Dynamic Functional Equivalency Checking with RTL Simulation
08: Functional Verification: The Good, the Bad, the Ugly
09: High Level Synthesis with NEC
10: System-on-Module for FPGA and ARM developers working on Internet of Things (IoT) Applications
Visit to register for a session of your choice.
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Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Emulation, Design Rule Checking, Clock Domain Crossing, VIP Transactors, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.  
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