The Signal Agent in VHDL allows you to monitor and drive VHDL signals from any VHDL block. Signals do not have to be routed via the interface or declared in global packages. This is particularly useful in test bench development and design verification.
Signal Agent allows driving VHDL records as well. Remember to use the dot separator to indicate record elements. For example: signal_agent( "/sub_top/a_top", "/sub_top/Label1/record1.a", 1 ); For details regarding Signal Agent implementation, search for keyword Signal Agent in the help manual.