I have migrated from Xilinx ISE™ to Xilinx Vivado™, and now I am not able to find certain components like fifo_generator, blk_mem_gen which were a part of the XilinxCoreLib library.
Xilinx Vivado no longer contains the XilinxCoreLib library. All the EDK and XilinxCoreLib components are now generated on the fly when the simulation is launched from the Vivado environment. Because of this, you have to set Active-HDL or Riviera-PRO as the default simulator in the Vivado software and use it as your primary IDE. For more information, refer to the following topics: