ELBREAD: Error: You do not have a valid license to simulate SystemVerilog assertion module


You are receiving the above error if your design is trying to use SystemVerilog Assertions, but this feature is not available in your license.


Please make sure that you are using a valid SystemVerilog Assertions license. Also check if SystemVerilog Assertions simulation feature is not being used by another user.

If you have a SystemVerilog Assertions license and are still receiving this error, please contact our support team through our Support Portal.

If your license does not have the SystemVerilog Assertions simulation feature, please disable the processing of assertions. You can disable the processing of assertion in the GUI by repeating the following steps:

  1. Select Design | Settings from the main menu

  2. Go to Compilation | Verilog | Assertions

  3. Select the All option in the Disable processing of assertions field

  4. Click Apply, then OK

  5. Compile the design and run the simulation.

If you are using scripts please add the –na all switch to the alog command.

Printed version of site: www.aldec.com/en/support/resources/documentation/faq/1754