Fatal Error: filename.sv: Bind: unresolved hierarchical reference to object "object name"


When I simulate my design, I receive the above error when binding between SystemVerilog and VHDL. How can I resolve this?


When binding between SystemVerilog and VHDL, please be sure to use the correct coding standard. For example:

bind <libary_name>.<entity/module_name>

is a VHDL library definition and will not work properly. You will need to use a direct instantiation:

bind <full_instance_path> <checker_entity/module_name> <checker_instance_name>

If you are still receiving this error, please create a case within our Support Portal.

Printed version of site: www.aldec.com/en/support/resources/documentation/faq/1738