HES-DVM supports all types of SCE-MI interfaces defined by the Accellera standard:
SCE-MI 1.0 Macro-Based Interface
Transactors that adhere to this standard have to instantiate predefined macro modules such as:
Message transport modules
Clock and reset modules
SCE-MI 2.0 Function-Based Interface
HES-DVM provides SCE-MI 2.0 SystemVerilog transactors compiler capable of translating DPI-C function exports and imports to SCE-MI message ports. After compilation and elaboration of such modules HES-DVM generates synthesizable code with SCE-MI infrastructure that can be implemented in the FPGA. HES-DVM also creates DPI-C linkage library that contains all necessary functions that might be used in the testbench.
SCE-MI 2.0 Pipes-Based Interface
The pipes-based interface fills the gap between the macro-based and function-based interfaces. It allows to achieve high throughput and provides a dynamically scalable channel with features like streaming data and variable length messaging. Ease of use is another big advantage of the pipes-based interface. It is sufficient to instantiate a predefined pipe-transactor in the HDL code and use its predefined C or SystemVerilog API in the testbench HVL code.