In the HES-DVM generated SystemC wrapper, there are some interface signals which are not in the list of I/O signals of DUT, what is the purpose of these signals?
Signals p0, p1,...p63 come from HES mapping file. This is how we reference each bit of DUT interface in hardware. Concatenation to real signals is done in SystemC or VHDL/Verilog wrapper.
2260 Corporate Circle
Henderson, NV 89074 USA
Tel: +1 702 990 4400
Fax: +1 702 990 4414
©2019 Aldec, Inc.
Printed version of site: www.aldec.com/en/support/resources/documentation/faq/1663