HES-DVM supports Hard-Macros (HM), which are technology dependent netlists. They have FPGA vendor proprietary format.
HM module is not synthesized during the design setup, but HES-DVM creates a black-box module in the design netlist. The HM netlist file is passed to the implementation tool as is and then linked with design netlist file. HES-DVM supports Xilinx hard-macro (*.ngc,*.ngd, *.ngo) files.