When I run a script in Riviera-PRO, I receive the above error. What does it mean and how can I fix it?
This is a generic message about a syntax error. In the code below, a semicolon (;) is missing after the name of the module. This triggers the VCP2000 message:
module m //VCP2000 endmodule
You can also receive the above error by using the alog/vlog commands when compiling VHDL files. Within the script that you are running in Riviera-PRO, please pay special attention to what command you use when compiling your design files. Verilog/SystemVerilog files need to be compiled using the alog/vlog command, and VHDL files need to be compiled using the acom/vcom command.
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