Language Neutral Simulation of Altera IP cores in Active-HDL


Altera provides some of its IPs (e.g. Transceiver PHY IP core) in Verilog or SystemVerilog form only. If you select VHDL for your transceiver PHY, only the wrapper generated by the Quartus II software is in VHDL. All of the underlying files are written in Verilog or SystemVerilog.


If your Aldec license file only includes the VHDL simulation feature, here is how you can enable the simulation of Verilog Altera IP cores:

  1. Your Aldec license file needs to include the Altera Language Neutral license feature. Check with your Aldec sales representative if you are not sure whether or not you have this feature.

  2. Contact your Aldec representative or open a ticket in our support portal and request to be provided with the language-neutral version of the desired Altera IP core. Aldec will watermark the original Verilog/SystemVerilog files of the Altera IP core to become language-neutral, and deliver them to you so you can simulate them only with VHDL and Altera Language-Neutral features.

NOTE: Aldec will only watermark Altera’s IP cores generated by Quartus II software. To simulate Verilog IP cores provided by third party vendors, you will have to have the Aldec Verilog simulation license.


The watermarking functionality will be available starting from Active-HDL 9.3 in September of 2013. Prior to that, early access can be provided with the patch per request. Please contact Aldec support.

Printed version of site: