It looks like one of the global clocks is a 200MHz reference clock, used when in emulation mode. For ASIC prototyping it looks like we really have 4 global clocks that can oscillate at 4 different frequencies. Is that correct?
The HES 7 board is equipped with:
PLL CLK_PLL clock module connected to FPGA0-2 globals clock inputs
PLL CLK_0 clock module connected to FPGA0-2 globals clock inputs
PLL CLK_1 clock module connected to FPGA0-2 globals clock inputs
PLL CLK_2 clock module connected to FPGA0-2 globals clock inputs
PLL CLK_3 clock module connected to FPGA0-2 globals clock inputs
200 MHz reference clock oscillator connected to all FPGA chips (FPGA_PROG, FPGA0-2),
PLL CLK_GTX block (for driving GTX blocks in FPGA0-2 chips
The HES7 board is equipped with a 200MHz reference clock for all FGPA chips + 5 clock modules connected to global lines in the FPGA0-2 chips (in other words - 5 global clocks) + an additional block for GTX modules clock driving.