Is there an equivalent to Questa's signal_spy functionality?

Description:

Aldec has a similar feature named Signal Agent. This feature can be used for VHDL, Verilog, or cross language designs.

The Signal Agent is implemented with the signal_agent procedure which is located in the signal_agent_pkg package in the pre-installed aldec library.

To use the signal_agent procedure, insert the aldec library and use clause:

library aldec;
use aldec.signal_agent_pkg.all;

The Signal Agent joins the source signal with the destination signal and the signal_agent procedure only needs to be called once.

Note: The aldec library clause only needs to appear in blocks or design units that use the signal_agent procedure.

VHDL Design

The Signal Agent in VHDL allows you to monitor and drive VHDL signals from any VHDL block.

Syntax

signal_agent(<source>,<destination>,<verbose>)

where:

<source> A quoted string specifying the name of the source signal or port. The name must be preceded with a full hierarchical path. The hierarchy separator may be either a slash or a dot.

<destination> A quoted string specifying the name of the destination signal or output port. The name must be preceded with a full hierarchical path. The hierarchy separator may be either a slash or a dot.

<verbose> Specifies if a message should be printed to the console when the signal_agent procedure is initialized. Use 1 to print the message, use 0 for quiet operation.

Example:

signal_agent("/uut/u1/signal_name", "signal_name",1);

Verilog Design

The $signal_agent task can be used to update Verilog or VHDL objects from Verilog code. This is useful for referencing VHDL objects in mixed Verilog-VHDL designs.

Syntax

$signal_agent(<source>,<destination>,<verbose>)

where:

<source> A quoted string that specifies the name of the source signal. Use a relative path or a full hierarchical path.

<destination> A quoted string that specifies the name of the destination signal. Use a relative path or a full hierarchical path.

<verbose> Specifies whether a message should be printed to the Console window when the $signal_agent task is initiated. Use 1 to print the message or 0 for a quiet operation.

Example:

$signal_agent("uut.u1.signal_name", "local_signal_name", 1);

Note: Please observe the difference in syntax for VHDL and Verilog signal agent declarations. VHDL uses "/" for hierarchy and Verilog uses "."

Cross Language Design

For more information, you can refer to:

Riviera-PRO
- VHDL: User's Guide | VHDL Simulation | Utility Routines | Signal Agent.
- Verilog: User's Guide | Verilog Simulation | Tasks and Functions | Signal Agent.
Active-HDL
- VHDL: Active-HDL Help | Using Active-HDL | Compilation | VHDL Compilation | Utility Routines | Signal Agent.
- Verilog: Active-HDL Help | Using Active-HDL | Compilation | Verilog Compilation | Signal Agent.