HES-DVM supports VHDL and Verilog and SystemVerilog hardware description languages. Mixed design style is also allowed, which is unique among design setup tools for in-hardware verification products. What distinguishes Aldec’s solution is also the native support for the EDIF netlist format and FPGA vendor hard macros.
HES-DVM provides interfaces for co-simulation in the SystemC environment and generates appropriate SC_MODULE wrappers for designs implemented in FPGAs. For designers using native C/C++, HES-DVM offers an API for the acceleration board and generates appropriate C++ wrappers for modules in FPGAs.