Specifying Verilog Library for Compilation

Description

I get this warning displayed when my design uses modules from a vendor library (Xilinx, Altera, Actel, Lattice, etc.):

Warning: VCP2515 <file name>.v : (563, 1): Undefined module: <library primitive> was used. Port connection rules will not be checked at such instantiations.

The simulator does not know which libraries to search for unknown modules. How can I fix it?

Solution

If you use GUI:

1. Go to Design | Settings | Compilation | Verilog

2. Locate Verilog Libraries window on the right-hand side. Click small yellow rectangle icon next to it.

1. Select proper library from the list and click Ok. To select multiple libraries at a time, hold Ctrl key.

2. Select Simulation | Verilog.

3. Locate the Verilog Libraries (-L) window on the right-hand side. Click small yellow rectangle icon next to it.

4. Select proper library from the list and click Ok. To select multiple libraries at a time, hold Ctrl key.

5. Click Apply button. Click Ok button.

6. Compile source files.

If you use batch mode/script:

Please add -l <library_name> argument to the ALOG macro command. You can also use the -L argument of the ASIM command to specify (while initializing the simulation session) the library that contains unknown units.

Example:
alog  -dbg  -l unisim_ver  -l secureip  my_file.