Port Assignment for FPGA/CPLD Chip


How to assign the input and output terminals easily to the ports of the development board? Is the only way to create an *.ucf file and choose this file in implementation options?


In general the pin list is provided by ucf constraints file. You can invoke the FPGA Editor after the mapping step and define the pins.

Another way to assign pins is to provide such constrains as VHDL/VERILOG attributes. You can select a port symbol (terminal) on bde and by pop-up menu select Properties | Attributes and define attribute for it.

Printed version of site: www.aldec.com/en/support/resources/documentation/faq/1134