No Code Coverage Data in results.ccl

Description

I am trying to use Code coverage but the results file is not showing any data.

Solution

You have to compile your design files with the enabled debugging switch.

  1. Go to Design | Settings | Compilation | Verilog(or VHDL) and check the Enable Debug option.

  2. Recompile your design files and rerun the simulation with Code coverage option enabled.

  3. You should see the code coverage statistics in results.ccl.



Printed version of site: www.aldec.com/en/support/resources/documentation/faq/1127