I have a testbench file in Verilog and the rest of my design is in VHDL. I wanted to force a value on a signal in VHDL part of the design and recieved the following error:
RUNTIME: Fatal Error: RUNTIME_0119 Invalid hierarchical access from Verilog instance "/" to non-Verilog object "/module_name/signal name".
VHDL does not allow hierarchical references, unlike Verilog. Therefore hierarchical references in Verilog cannot point to VHDL objects. You need to use $signal_agent task to access VHDL signals from the Verilog code.
Here is syntax of $signal_agent task:
$signal_agent (<source>, <destination>, <verbose>)>
<source> A quoted string that specifies the name of the source signal. Use a relative path or a full hierarchical path.
<destination> A quoted string that specifies the name of the destination signal. Use a relative path or a full hierarchical path.
<verbose> Specifies whether a message should be printed to the Console window when the $signal_agent task is initiated. Use 1 to print the message or 0 for a quiet operation.
Note: The $signal_agent task is located in the systf.dll library. The library must be included in the list of PLI applications visible to the environment for the $signal_agent task to work. The systf.dll library is located in the \Bin subdirectory of the Active-HDL installation folder.