I know I can force signal values with force command. But what should I do if I would like to have the signals overdriven by the logic from design again?
You may use a release command in addition to force. A force procedural statement on a net shall override all drivers of the net—gate outputs, module outputs, and continuous assignments—until a release procedural statement is executed on the net. When released, the net shall immediately be assigned the value determined by the drivers of the net.
You may find additional information about force and release in Active-HDL Help Index tab | type force or Verilog Standard.
Console Command: force -help.