I received above message during compilation. How can I fix it?
This is the internal error message that comes from Aldec's Verilog compiler. In order to solve this issue you may try the following:
Right-click on your working library in the Design Browser and empty it by selecting “Delete simulation data” from the pop-up menu.
Recompile the design.
If you get the same error message again, please open a support ticket at http://www.aldec.com, and attach either specifically the file for which the error was reported or the entire design.