What is the difference between a Vital Model and Vital Library?

Vital Model defines how ASIC libraries should be specified in Vital-compliant VHDL in order to be simulated in VHDL simulators.

This covers in particular:

Vital libraries contain primitives (structural) and other behavioral components adhering to the modeling specifications.

Printed version of site: www.aldec.com/en/support/resources/documentation/faq/1028