In the Active-HDL Design Browser, I expanded the top level HDL source file and then right-clicked on its entity/architecture to select it as top level for simulation. Unfortunately, the request to set top-level is not executed. Running Synthesis in the Design Flow then fails with the above error in Active-HDL console window.
When you select a top-level in the Design Browser, it only sets the top-level for the simulation. This setting doesn’t affect synthesis.
In order to specify the top-level for synthesis please follow these steps:
Go to the Design Flow (click “design flow” tab at the bottom)
Click on the small “options” button located on the left side of Synthesis button.
In the ‘Synthesis Options” window go to the General tab.
In the “Top-level Unit” field select top-level module for synthesis from the drop-down list.
The reason you might be getting this error is because nothing is specified in the “Top-level Unit” field.