Cannot Debug Source Code. Cannot Set Breakpoints.


This warning Warning: DAGGEN_0523: The source is compiled without the -dbg switch. Line breakpoints, code coverage, and assertion debug will not be available. is displayed when I attempt to simulate the design. I cannot see all of the signals in the structure browser window for the design. I am getting a "Cannot set breakpoints" message from the tool while trying to set a code breakpoint.


By default, the Aldec simulator optimizes your design for the fastest simulation performance possible. That will affect debug access and signal visibility. You need to enable the following debug settings while compiling your files and initializing your simulation.

VHDL and Verilog Compilation

For both VHDL and Verilog compilation you must set the compiler to the debugging mode.

Recompile all your source files

Simulation Initialization (Verilog only)

This step is only necessary for Verilog or Mixed Language designs

Initialize your simulation and you should be able to set your breakpoints in your code. Just make sure that you are setting your breakpoint on the executable statements of your code.

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