Starting Active-HDL as the Default Simulator in Altera Quartus II

Introduction

Active-HDL simulator can be run directly from Altera® Quartus software using NativeLink feature. This application note explains how to use the NativeLink feature in Altera Quartus II. This application note has been verified on Active-HDL 10.3 and Quartus 16.1. This interface allows users to run mixed VHDL, Verilog and System Verilog (“design” constructs) simulation using Active-HDL as the default simulator.

Configuring Active-HDL in Quartus II

Figure 2 EDA Tool Settings in Quartus II

NativeLink Settings

NativeLink settings are located at the bottom of Simulation category on the right hand side, as shown in Figure 3. There are three NativeLink settings for selecting the test bench for the simulation.

Figure 3 EDA Tool Settings

Now select the option of your choice from NativeLink Settings. For Running the simulation, please refer to the next section. For more details on these options please click on the link at the end of this application note.

Running the simulation

To launch Active-HDL from Quartus II, click on Tools | Run Simulation Tool | RTL Simulation option. Active-HDL starts and creates the project and adds necessary files to the project. It also creates and compiles the necessary Altera libraries. It adds signals to the waveform and runs simulation after that. You will receive the end of the simulation message in the console when simulation is done as shown in Figure 4.

Figure 4 Running Simulation

Figure 5 Running Simulation

More information

For detailed information on starting and running Active-HDL simulator from Quartus II software please visit, http://www.altera.com/literature/hb/qts/qts_qii5v3.pdf.



Printed version of site: www.aldec.com/en/support/resources/documentation/articles/995