Performing Functional Simulation of Xilinx Zynq BFM in Riviera-PRO


The Zynq-7000 bus functional model (BFM) is created by Xilinx™ to support the functional simulation of Zynq-7000 based applications. It enables the functional verification of Programmable Logic (PL). This BFM mimics the Processing System (PS), Programmable Logic (PL) interfaces, and memories of PS logic.

Requirements and Limitations

As there is no PL in this scenario, Cadence AXI BFMs are used to mimic the PL. These BFMs are connected to individual AXI ports in Zynq-7000 BFM. This application note assumes the following:

  1. You have a Xilinx Zynq-7000 device and Vivado Design Suite 2014.4 or later.

  2. You have a Riviera-PRO version 2014.10 or later licensed and installed properly.

  3. You have an AXI license (AXI BFM simulation model) and IP Integrator license for VIVADO.

  4. Make sure that Riviera-PRO has the required Xilinx simulation libraries. Required libraries are unisims_ver and secureip (axi_bfm included).

  5. Download the example design zynq_bfm_example.tar.gz from the Xilinx website. Please follow the instructions provided in this document to setup the example design in Vivado.

NOTE: The editions of Xilinx Vivado and Riviera-PRO must be compliant. If you are using the 64-bit edition of Riviera-PRO, select the 64-bit Vivado. If you are using the 32-bit edition, select the 32-bit Vivado version. To run the 32-bit version, pass the -m32 argument to the vivado.bat file when starting the Vivado software.

Enabling Aldec Simulator in Xilinx Vivado

  1. In the c:\Users\<user_name>\AppData\Roaming\Xilinx\Vivado or <home_directory>/.Xilinx/Vivado directory, for the Windows or Linux platform, respectively, find or create the init.tcl file and append the following line to it:

    set_param project.enableAldecUnifiedFlow 1
  2. In the Vivado environment, open the Xilinx Tcl Store with the Xilinx Tcl Store option available in the Tools menu and click the Refresh button present on the bottom of the window. This will update the list of the applications available in the store.

  3. The Riviera-PRO Simulator application should be present on the list. Click the Install button next to it to enable the Aldec simulator.

Running Zynq BFM Simulation

Make sure to follow all of the requirements given above before starting the steps below.

  1. Add the <Riviera-PRO_installation_path> path to your %PATH% environment variable. To confirm that you have the %PATH% variable set correctly, open the windows command prompt, type "path", and press ENTER. Then check if the path to the Riviera-PRO installation directory is present in the command output.

    Figure 1: Checking the PATH system variable

    NOTE: If Vivado is already running while you add the path, then you will have to restart Vivado to have your new PATH variable effective inside Vivado.

  2. Make sure that the example design is properly set in Vivado. The Block Design of the zynq system is similar to what is given in Xilinx AR#55345.

  3. In the Flow Navigator, click on Simulation Settings under the Simulation section which will open the Project Settings window. Make sure that Target language is Verilog under the General category.

    Figure 2: General Project Settings

  4. Select the Simulation category in the Project Settings window. In this category under the Compilation tab, change Target simulator to Riviera-PRO Simulator. Add +define+XILINX_ISIM in the riviera.compile.vlog.more_options field and select the checkbox next to the riviera.compile.debug field. The latter option will enable the debugging capability during simulation and will allow you to use the debugging tools of Riviera-PRO.

    Figure 3: Compilation options

  5. Now under the Simulation tab, set the -all value in the riviera.simulate.runtime field. This will advance the simulation until no simulation events are scheduled or the simulation is stopped by a code or a signal breakpoint.

    Figure 4: Simulation options

    NOTE: If a version of Riviera-PRO was updated between subsequent simulation runs, you should use the Clean Up Simulation files option available in the Simulation category of the Project Settings window to remove the files generated with the previous version of the Aldec simulator.

  6. In the Flow Navigator, click on Run Simulation and then Run Behavioral Simulation to launch Riviera-PRO from Vivado. This action will create .do scripts with the commands necessary to compile the design and run simulation.

    Figure 5: Launching Riviera-PRO

  7. As soon as Rivera-PRO is launched, break the current operation by clicking the "Red Cross" button in the toolbar. This will stop Riviera-PRO from executing the script generated by Vivado for the Zynq BFM simulation. This is necessary as the script requires minor changes before it can be run in Riviera-PRO.

    Figure 6: Breaking current operation

  8. Locate and open the script in your design folder.

    Figure 7: Opening script

    In the script, add the following commands to map the secureip and unisims_ver libraries:

    amap secureip "$aldec\\vlib\\xilinx_vivado\\secureip\\secureip.lib"
    amap unisims_ver "$aldec\\vlib\\xilinx_vivado\\unisims_ver\\unisims_ver.lib"

    In the asim command, replace the libxil_vsim.dll library with libxil_riviera.dll. Depending on the edition of Riviera-PRO and Vivado (either 32 or 64 bit), select the appropriate version of the library:

    • The 32-bit version is stored in the C:/Xilinx/Vivado/2014.4/lib/win32.o directory.

    • The 64-bit version is stored in the C:/Xilinx/Vivado/2014.4/lib/win64.o directory.

    For the 64-bit edition of Riviera-PRO the asim invocation should be as follows:

    asim -t 1ps +access +r +m+test -L unisims_ver -L unimacro_ver -L secureip -L xil_defaultlib -O5 \
    -pli "C:/Xilinx/Vivado/2014.4/lib/win64.o/libxil_riviera.dll" xil_defaultlib.test xil_defaultlib.glbl
  9. Rename the script (use File | Save As to save it with a different name). This action is required because every time you change the design in Vivado and launch Riviera-PRO again, this script is overwritten.

  10. Execute the script. Observe the simulation results on the waveform. The Console output should look like the one below.

    Figure 8: Simulation results


Xilinx Zynq-7000 BFM simulation can be successfully run in Riviera-PRO. To get detailed information about Zynq-7000 BFM, refer to the following link:

If you have difficulty simulating Zynq-7000 BFM in Riviera-PRO, please contact Aldec Support through the customer portal.

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