Simulating a Design with Xilinx Libraries (UNISIM, UNIMACRO, XILINXCORELIB, SIMPRIMS, SECUREIP)

This application note provides a quick overview of Xilinx®-targeted simulation flow based on Aldec’s design and verification environments, Active-HDL™ or Riviera-PRO™; detailed information can be found in the following Xilinx documents:

Conceptual Overview

Simulation can be applied at several points in the design flow (Figure 1). It is one of the first steps after design entry and one of the last steps after implementation as part of the verifying the end functionality and performance of the design.

Figure 1: Xilinx Simulation Flow

Xilinx Simulation Libraries Overview

When you instantiate a component in your design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation. (Table 1 lists Xilinx simulation libraries).

Table 1: Xilinx Simulation Libraries

Library Name


VHDL Library Name

Verilog Library Name


Used during functional simulation and contains descriptions for all the device primitives, or lowest-level building blocks




Used during functional simulation and contains macro descriptions for selective device primitives




An optional library that can be used during RTL behavioral simulation to speed up simulation runtime




Used during RTL Behavioral simulation for designs containing certain cores created by the Xilinx IP catalog




Used for simulating timing simulation netlists produced after synthesis or implementation. (Verilog UNISIM with timing)




Used for functional and timing simulation of complex FPGA components, such as PCIe® IP, Gigabit Transiever



You must specify different simulation libraries according to the simulation points. (There are different gate-level cells in pre- and post-implementation netlists). Table 2 categorizes the libraries by simulation points.

Table 2: Xilinx Libraries Required in Simulation Points

Simulation Point

Required Library

Register Transfer Level (RTL)






Post-Synthesis Simulation

UNISIM (Functional Netlist)

SIMPRIMS_VER (Timing Netlist)


Post-Implementation Simulation

UNISIM (Functional Netlist)

SIMPRIMS_VER (Timing Netlist)


Compiling Xilinx Simulation Libraries for Aldec

There are several ways to compile and attach Xilinx simulation libraries, depending on Xilinx tool you use:

  1. Xilinx Vivado (compile_simlib): Use the compile_simlib Tcl command in the Vivado Design Suite Tcl Console for compiling Xilinx HDL-based simulation libraries for Aldec. When this command is run with a project open, the tool will use the device family, target language, and library settings specified by the project as the default values, rather than the default settings of the command; the default settings can be overridden by specifying the necessary options when the command is run.

    NOTE: Xilinx recommends using the UNIFAST library for initial verification of the design and then running a complete verification using the UNISIM library; the simulation runtime speed-up is achieved by supporting a subset of the primitive features in the simulation mode.

    The following example shows how to compile UNISIM and SIMPRIM (VHDL) libraries for Aldec for a design using a Virtex®-7 device:

    compile_simlib -simulator riviera -family virtex7 -library unisim -library simprim -language vhdl
    compile_simlib -simulator active-hdl -family virtex7 -library unisim -library simprim -language vhdl

    (Refer to Xilinx’s UG894 Tcl Command Reference for detailed instructions on how to use this command).

    NOTE: Libraries are typically compiled (or recompiled) anytime a new simulator version is installed or when you update to a new version of the Vivado IDE.

  2. Xilinx ISE (compxlib): Use the compxlib tool for compiling the Xilinx® HDL-based simulation libraries. For example, the following commands compile all Xilinx® Verilog libraries for the Virtex®-6 device family on Aldec simulators:

    compxlib -s riviera -arch virtex6 -l verilog
    compxlib -s active_hdl -arch virtex6 -l verilog

    (Refer to Xilinx’s UG628 Command Line Tools for detailed instructions on how to use this command).

    NOTE: Libraries are generally compiled or recompiled anytime a new version of a simulator is installed, a new ISE version is installed, a new service pack is installed, or when a new IP Update is installed.

Alternatively, you can also download the precompiled Xilinx simulation libraries from (Select the Aldec product you use to see the precompiled libraries for that specific product/version).

NOTE: If you use a VHDL-only Active-HDL or Riviera-PRO configuration, you must download the SECUREIP library from Aldec website; since Xilinx’s SECUREIP contains sources in Verilog, Aldec provides a special watermarked version of the SECUREIP to enable simulation with VHDL-only license; refer to Language Neutral Libraries with Xilinx application note for more details.

Running Aldec Tools from Xilinx GUI

The following sections (Running RTL/Behavioral Simulation, Running Netlist Simulation, Running Timing Simulation) provide a quick reference for running a simulation outside of Xilinx’s GUI. Alternatively, you can start Aldec Active-HDL or Riviera-PRO and run an RTL/Behavioral, Netlist, or Timing simulation directly from the Xilinx graphical environment; refer to the following application notes for details on how to set Aldec as default simulator:

Running RTL/Behavioral Simulation

  1. Compile simulation libraries as explained in the previous section Compiling Xilinx Simulation Libraries for Aldec.

  2. Compile sources and testbench files.

    NOTE: If you use Verilog, you must compile glbl.v as well (Xilinx® devices have dedicated routing and circuitry that connect to every register in the device; see Xilinx’s UG900 Logic Simulation for details).

  3. Simulate the design. Make sure to correctly reference the libraries necessary for proper simulation, for example:

    vsim -t ps -L secureip -L unisims_ver work.<testbench> work.glbl

    NOTE: Xilinx recommends that you run simulations using a resolution of 1ps. Some Xilinx primitive components, such as DCM, require a 1ps resolution to work properly in either functional or timing simulation.

Running Netlist Simulation

  1. Compile simulation libraries as explained in the previous section Compiling Xilinx Simulation Libraries for Aldec.

  2. Compile sources and testbench files. (If you use Verilog, you must compile glbl.v as well).

    NOTE: The simulation testbench used for RTL/Behavioral simulation can be reused.

  3. Generate simulation netlist:

    • Xilinx Vivado:

      • For a functional netlist, use write_verilog -mode funcsim

      • For a timing netlist, use write_verilog -mode timesim

      • For SDF, use write_sdf


      synth_design -top top -part xc7k70tfbg676-2 -flatten_hierarchy none
      open_run synth_1 -name netlist_1
      write_verilog -mode funcsim test_synth.v
      write_verilog -mode timesim -sdf_file test.sdf test_synth_timing.v
      write_sdf test.sdf

      Now, you can use test_synth.v for functional simulation or test_synth_timing.v for timing simulation with test.sdf.

      (Refer to Xilinx’s UG894 Tcl Command Reference for detailed instructions on how to use this command).

    • Xilinx ISE (XST):

      • For a functional netlist, use:

        netgen -ofmt {verilog|vhdl} [options] input_file[.ngd|ngc|ngo]
      • For a timing netlist and SDF, use:

        netgen -sim -ofmt {verilog|vhdl} [options] input_file[.ncd]

        (Refer to Xilinx’s UG628 Command Line Tools for detailed instructions on how to use this command).

  4. Simulate the design.

Running Timing Simulation

  • Timing simulation uses the SIMPRIM library; ensure that you are referencing the correct libraries during the timing simulation process.

  • Timing simulation requires you to pass in additional switches for correct pulse handling; the following switches must be added to the simulation initialization command:

    +transport_int_delays – selects transport mode for interconnect delays.

    +pulse_int_e/0 – specifies the pulse error limit as a percentage of the Verilog interconnect delay.

    +pulse_int_r/0 – specifies the pulse rejection limit as a percentage of the Verilog interconnect delay.

Additional Resources

For Support resources such as Application Notes, FAQs, Documentation, Downloads, and Recorded Webinars, visit Aldec's Resource page as well as Xilinx Support.

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