This document describes how to start the Riviera-PRO simulator from Xilinx Vivado™ to run behavioral and timing simulations. This application note has been verified on Riviera-PRO 2017.10, Xilinx Vivado 2017.3, and Active-HDL Simulator 1.12 add-on to Vivado. This integration allows users to run VHDL, Verilog, Mixed, and SystemVerilog (Design) simulations using Riviera-PRO as the default simulator.
In order to run the simulation successfully, depending on the design, both VHDL and Verilog simulation libraries for the respective Xilinx Vivado version may have to be installed in Riviera-PRO. You can check which libraries are currently installed in the Libraries window. The tool can be accessed by selecting the Libraries option available in the Design Management Windows category of the View menu. Libraries have to be compiled for the Riviera-PRO version you are using for simulation.
You can compile Xilinx libraries from sources with the compile_simlib command of Vivado.
NOTE: After generating the compiled libraries from Xilinx, they have to be manually attached to Riviera-PRO. For more information refer to Compiling Xilinx Vivado Simulation Libraries for Riviera-PRO.
You can also install precompiled libraries:
If you have received a web link to download Riviera-PRO, on the same page, you will find the links to download Xilinx libraries.
At any time you can visit the update center to download the latest Xilinx libraries at http://www.aldec.com/en/downloads.
If you do not find the library matching the Xilinx version in the above link, then please create a support case in the Support Portal and request a library with Xilinx and Riviera-PRO version numbers.
Add the <Riviera-PRO_installation_path>\bin path to your %PATH% environment variable. To confirm that you have the %PATH% variable set correctly, open the windows command prompt, type "path", and press ENTER. Then check if the path to the Riviera-PRO installation directory is present in the command output.
NOTE: If Vivado is already running while you add the path, then you will have to restart Vivado to have your new PATH variable effective inside Vivado.
Select the Xilinx Tcl Store option from the Tools menu, switch to the Installed tab, and make sure that the Riviera-PRO Simulator plug-in is already installed. If it is not, find the plug-in under the All tab and click the Install button. If the plug-in is already installed, you can update it to the latest version. To do so, click the Update button after refreshing the repository with the Refresh button.
Create or Open a project in Xilinx Vivado Project Manager.
From Flow Navigator, click on the Simulation Settings item.
Under the Simulation category of the Project Settings window, change the Target Simulator to Riviera-PRO Simulator.
Here under the Compilation tab, you can pass arguments to the Verilog and VHDL compiler.
NOTE: You may need to select the riviera.compile.vhdl_relax checkbox that relaxes some LRM requirements when compiling VHDL files.
Under the Elaboration and Simulation tabs you can set simulation related arguments e.g. logging all signals to simulation database, accessing signals for waveform, or simulation run time.
Once all options are set according to your requirements, click OK.
NOTE: If a version of Riviera-PRO was updated between subsequent simulation runs, you should select the Clean up simulation files check box available in the Simulation category of the Project Settings window to remove the files generated with the previous version of the Aldec simulator.
Now, click on the Run Simulation tab from the Flow Navigator and select the type of simulation you want to run.
This will launch Riviera-PRO. Vivado will generate DO macro scripts for compilation and simulation based upon the settings you provided in the above steps.
Riviera-PRO will start executing the automatically generated DO macro, and will launch the Waveform Viewer with the signals loaded.