Language Neutral Libraries with Xilinx®


Xilinx® first started using the SecureIP methodology for IP delivery. These IPs were written using Verilog and SystemVerilog which required a Verilog license for simulation. For the users with a mixed language or Verilog license, this was not an issue. Unfortunately this was an issue with VHDL-only license owners.

Aldec has worked with Xilinx® to provide language neutral libraries that allow users with a VHDL-only license to simulate designs with an IP that contains Verilog/SystemVerilog without purchasing a separate Verilog license. These language neutral libraries are watermarked for VHDL-only customers and can be downloaded from the Aldec website. Please note that VHDL-only customers will need the Language-neutral libraries feature added to their license file in order to use these libraries successfully. Please contact to enable this feature.

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