Some of the IPs that Altera® provides have embedded Verilog/SystemVerilog IPs, which requires a Verilog license for simulation. For the users with a mixed language or Verilog license, this is not an issue. Unfortunately, users with a VHDL-only license could not simulate these IPs as it requires a Verilog simulation license.
Aldec has worked with Altera® to provide language neutral libraries that allow users with a VHDL-only license to simulate designs with an IP that contains Verilog/SystemVerilog without purchasing a separate Verilog license. These language neutral libraries are watermarked for VHDL-only customers and can be downloaded from the Aldec website. Please note that VHDL-only customers will need the Language-neutral libraries feature added to their license file in order to use these libraries successfully. Please contact firstname.lastname@example.org to enable this feature.