Every advanced Design Rule Checking (DRC) tool has its own built-in synthesis engine which provides information to complex chip-level design rules. But regular approach to synthesis is not effective for FPGA vendor components/primitives because they contain non-synthesizable code. But ALINT has a unique solution for this problem – native support for most commonly used libraries from Xilinx® and Altera® – this application note explains how it works.
Schematic libraries for FPGA include the following types of symbols (also referred to as components):
Primitive – a resource which is directly recognized by implementation software and typically corresponds to a logic resource in a target FPGA (e.g. I/O pins, buffers, logic gates, or flip-flops).
Macro – a schematic which contains primitives and other macro that implement more complex predefined functions (e.g., counters, shift registers, decoders).There are two types of macro – soft and hard. Soft macros have predefined functionality but their physical implementation depends on the implementation software. Hard macros have predefined mapping and placing information – their implementation is optimized.
Typical FPGA library contains wide and extensive variety of primitives and macros – starting with simplest buffers and two-input gates to comparatively complex things such as accumulators or RAMs
Regular approach to synthesis is not effective for vendor components because they contain non-synthesizable code. This is software implementation's task to match a component with the appropriate logic resources. With regular synthesis, vendor components are treated as black boxes which basically cause the following problems:
False violations are reported by various rules (e.g. rules that check connections to black box I/Os, or detect issues related to controllability from external input ports, or investigate combinatorial feedbacks).
Information about design hierarchy remains incomplete. Chip-level rules cannot properly analyze interconnections between the design elements and important design flaws may remain unaddressed.
Regular approach to synthesis is illustrated in Figure 1:
Point #1. The SIG signal is connected to the black box input – further propagation of this signal to the other parts of the circuit is blocked. Therefore the signal might not be recognized as a clock or reset even if it is actually used for that purpose – this may result in false or missing rule violations.
Point #2. The output of this black box is connected to the clock pin of the flip-flop – this results in another false violation related to the improper clock source.
Figure 1: Regular Approach to Synthesis
In order to handle vendor components properly, the linting tool needs to be aware about their internal structure and functionality. When the internal structure is known, it is possible to substitute a vendor component with equivalent model for synthesis and to avoid generating a black box.
Each vendor library can include components with one of the following three levels of support – the level of the tool awareness about internal structure:
Full – ALINT is fully aware of internal structure of a component (interface and logic inside – white box). An example of fully supported primitive handling is shown in Figure 2:
Point #1. The SIG signal is auto-detected as a clock because it is connected to the clock pin of supported vendor primitive.
Point #2. The illegal connection of the flip-flop output to the clock pin of another flip-flop is detected. (Unlike in a case when primitive is not supported and false black box related violations are reported).
Figure 2: Full Native Support for Primitives
Simplified – some primitives have quite complex internal structure and are not replaced by completely equivalent logic models; FIFOs, RAMs, and LUTs fall into this category. This means that all he Chip-Level rules treat these primitives as gray boxes (special type of black box which is transparent for combinational feedbacks, clocks, and resets). An example of simplified support is shown in Figure 3:
Point #1. The output of FIFO16 is auto-detected as a clock and recognized in the rest of the circuit appropriately.
Point #2. There is no false black box related violations for connection of FIFO16 output to the clock pin of the flip-flop.
Figure 3: Simplified Native Support for Primitives
Special – some primitives such as clock generators (DCM, PLL) and random access memories (RAM) cannot be replaced by equivalent logic models – and in this case it is not necessary for the tool to be aware of their internal structure. But their interface still matters – this means that clock generator outputs are treated as global clocks in the design and their frequency relationship is also taken into the account. A vendor primitive which has multiple clock outputs may infer more than one clock domain. (A clock output of a DCM infers a separate domain if this output does not have constant frequency and phase relationship with an input clock). An example of special support is shown in Figure 4:
Figure 4: Special Native Support for Primitives
The following list summarizes levels of vendor primitive support in ALINT:
Full – white box
Simplified – gray box
Special – interface only
Unsupported primitives are treated as black boxes. The details about supported libraries are available in the tool documentation (User's Guide | Advanced Features | FPGA Vendor Primitives | Supported Libraries). The following vendor libraries are fully supported:
Xilinx – unisim, ovi_unisim, simprim, ovi_simprim.
Altera – altera, ovi_altera, lpm, ovi_lpm, cycloneive , ovi_cycloneive.
The following steps must be performed to attach a precompiled vendor library:
Click the Attach Library button in the Library Manager.
Type a new library name in the appropriate edit box.
Point the tool to a pre-compiled library file (.lib).
The precompiled libraries are available for download from our support portal at http://support.aldec.com. Once a library is attached, it appears in the Library Manager and is ready to use – no additional actions required – supported vendor primitives are recognized automatically.
Please also note that you can build a library from the source files. Search for “Using ALINT with Aldec and third-party simulators” in our Knowledge Base if you need more details on this.
Native support for vendor libraries is a unique solution that significantly improves accuracy of FPGA designs analysis:
No black boxes а the amount of false and misleading violations is substantially reduced.
Complete hierarchy а important warnings from Chip-Level rules are not missing.
Major libraries from Xilinx and Altera are already supported but full support for any other libraries can be added on request – contact email@example.com.
ALINT 2012 Windows
ALINT 2012 Linux