Active-CAD is a completely integrated suite of EDA tools for the development of FPGA /CPLD designs. It supports various design entry and simulation methods. A design can be entered via schematic, HDL, or State Machine. These designs can be pure schematic, mixed mode (combining schematics, HDL, and State Machine macros) or HDL centric (pure HDL, or State Machines.)
Active-HDL provides a utility for importing Active-CAD/Foundation schematics (*.sch), libraries, and complete projects. The import utility allows Active-CAD/Foundation users to migrate their current and legacy projects and designs into Active-HDL design environment.
Active-HDL supports importing both Schematic-type and HDL-type projects. Projects containing ABEL files or state diagram files targeted to ABEL attached as top-level documents cannot be imported.
Before importing an Active-CAD project, you should create a new empty design in Active-HDL. The import is initiated by the Import>Active-CAD Project command from the File menu. The command starts a process as a result of which some of the original Active-CAD project files are copied into the current design (in Active-HDL) while the others are converted. The import preserves the hierarchical structure of Active-CAD schematics. During the import, you will notice Active-CAD programs running as minimized tasks.
The table below describes the way schematic-type projects are imported.
In an HDL-type project, files of any type (schematics, VHDL, Verilog, and ABEL) can be attached to the Project's Manager Hierarchy Browser. During the import, the following operations are performed:
All VHDL and Verilog files attached to the original project are copied and attached to the Active-HDL design.
All schematic files attached to the original project are converted to block diagram. The resulting block diagram files are added to the Active-HDL design. If the Active-CAD project includes several schematic files attached, the files are converted individually and are not merged into a multi-page block diagram.
During the import, Active-HDL creates a master log (in the HTML format) plus a number of partial logs (in a plain text format). The master log is attached to the imported Active-HDL design so that you can open it directly from Design Browser. It contains links to the partial logs.
Instead of importing the whole Foundation project, you can import individual schematics. During the import, a schematic file is converted into a block diagram and automatically added to the current Active-HDL design. All user-defined macros appearing on the imported schematic are converted to empty symbols. Only system macros are converted according to the rules for importing schematic-type projects.
Active-HDL allows you to import the contents of an Active-CAD library. The source files describing macros residing in the imported library are automatically attached to the current design, and then compiled. The rules for importing macros are identical to those for importing schematic-type projects.
Active-CAD users switching to Active-HDL will notice a number of functional differences between these two tools. The table below describes all major differences and can be helpful in addressing problems occurring in imported Active-CAD and Foundation projects.
The HDL code exported from Active-CAD designs contains instances of components whose simulation models must be included in one of the HDL libraries available in Active-HDL. Active HDL provides compiled libraries of simulation models for most popular FPGAs and CPLDs. Most of them include source code for debugging purposes. Note that these libraries have copyright restrictions and you cannot either modify or distribute their source.
Active-HDL provides libraries for the following vendors:
HDL code exported from Active-CAD designs for the above listed vendors can be simulated in Active-HDL without any additional adjustments.
Additional libraries can also be added to Active-HDL if you obtain their source from a PLD vendor.
If the exported design has been previously developed and simulated in Active-CAD, simulation test vectors can be re-used for simulation in Active-HDL. Test vectors must be saved in the ASCII format (*.ASC) - Active CAD uses two formats of test vector files: binary and ASCII. In addition to signal waveforms, the ASCII files include information about stimulators as they have been defined in the Waveform window.
In Active CAD, save waveforms in the ASCII format by using the File/Save Waveform command with the ASCII Test Vectors option.
In Active HDL, open the file using the File /Open menu command. The operation will restore waveforms as they have been saved in the file and will convert stimulators specific to the Active-HDL format.
If COREGen and LogiBLOX components are instantiated in VHDL or Verilog files in HDL-type projects, their corresponding EDIF netlist files will not be imported.
HDL-type projects with ABEL files attached cannot be imported.
If you have defined stimulators in the Waveform Editor window during functional simulation, and then reinitialize the simulator for post-synthesis or timing simulation, the stimulator will disappear.