Getting Started with Active-HDL


This tutorial provides instructions for using the basic features of the Active-HDL simulator. Active-HDL is an integrated environment designed for development and verification of VHDL, Verilog, System Verilog, EDIF, and System C based designs. In this tutorial we use a sample VHDL design called PressController from the Active-HDL installation to perform design entry and simulation.

Getting Started

You will first need to install latest version of Active-HDL on your computer to be able to successfully complete this tutorial. It is available as a free download from

Creating Workspace and Design

In Active-HDL, individual designs along with their resources (source files, output files with simulation results, etc) can be grouped together as a workspace. The workspace allows adding and working with several designs simultaneously

Creating/Adding Files to design

Creating HDL Source Code

If you want to create VHDL/Verilog/System C Source file, double-click the Add New File option and choose the correct source file type. A new editor window will open on the right hand side of the Design Browser. Text-based design entry will look like Figure 6.

Figure 6 Creating a VHDL Code File

Creating a new State Diagram in State Diagram Editor

Adding Ports to diagram

Adding signals or variables to the diagram

Adding States to the Diagram

Drawing Transitions between states

After adding everything explained above, your State Diagram will look like Figure 7.

Figure 7 State Diagram

Creating a new Block Diagram in Block Diagram Editor

Adding Symbols in Block Diagram

Adding New Wires

There are two methods of drawing wires. The first method is based on consecutive clicks and the other requires that you hold the mouse button while drawing.

  1. Go to the Diagram menu click on the Wire.

  2. Click where you want start drawing the wire.

  3. Move the mouse pointer toward the point where you want to end the wire. When moving the mouse pointer, a temporary wire line will be stretched between the wire origin and the current location of the mouse pointer. If you want to anchor a corner on the wire being drawn, click with the mouse button.

  4. Click where you want to end the wire. If you want to end the wire in empty diagram space, you must double-click instead of the single click.

  5. To draw another wire, repeat steps 2 to 4.

To draw a new wire using the method with the pressed-in mouse button

  1. Go to the Diagram menu click on the Wire.

  2. Move the mouse pointer to the point where you want to start drawing the wire, and then hold down the mouse button.

  3. While holding the mouse button, move the mouse pointer toward the point where you want to end the wire. When you move the mouse pointer, a temporary wire line will be stretched between the wire origin and the current location of the mouse pointer. To anchor a corner on the wire being drawn, press Space while still holding the mouse button.

  4. Release the mouse button to end the wire.

  5. To draw another wire, repeat steps 2 to 4.

Adding New Buses

Drawing new bus is similar to drawing new wire. You have to select Bus instead of Wire from the Diagram menu and repeat steps 2 to 4 of Adding New Wires.

Adding New FUB

Adding a new FUB (Functional Unit Block) is also similar to drawing new wire. You have to select FUB instead of Wire form Diagram menu and repeat steps 2 to 4 of Adding new wires.

After adding everything, your Block Diagram will look like Figure 8.

Figure 8 Block Diagram

Generating Testbench

The Testbench Wizard is designed for automatic generation of testbench files (one macro file and a number of source files) based on the user-defined specification. One of the most important information entered by the user is the test vector file name. A testbench generates stimulus for the UUT entity on the basis of test vectors defined in this file.

The Testbench Wizard accepts the following file types:

For generating a Testbench:


Compilation is a process of analysis of a source file. Analyzed design units contained within the file are placed into the working library in a format understandable to the simulator. In Active-HDL, a source file can be VHDL file/ Verilog file/ EDIF netlist file/ State diagram file/ Block diagram file.

In case of a block or state diagram file, the compiler analyzes the intermediate VHDL, Verilog, and EDIF file containing HDL code (or netlist) generated from the diagram ($dsn\compile). Active-HDL provides three compilers, respectively for VHDL, Verilog, and EDIF. When you choose a menu command or toolbar button for compilation, Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled.

Compiling Files


  • All messages (infos, warnings and errors) generated during compilation are displayed in the Console window or if enabled, on the Compilation tab.

  • Library units resulting from the compilation of a source file are placed into the working library selected for this file. By default, all source files in the design will be compiled into the default working library.

Initializing the Simulation

Once all needed design units have been successfully compiled, you can initialize simulation. Before you initialize simulation, make sure that:

If you run the simulator without any top-level unit selected, Active-HDL will prompt you with a dialog box to select one.

To begin simulation, you must choose Initialize Simulation from the Simulation menu. The command launches elaboration and initialization of the simulation model. During elaboration, the simulator loads design units and builds the simulation model in the computer memory. During the initialization, all objects in the model (signals, variables, etc.) acquire their initial values (either default or explicitly specified) and all concurrent processes are executed once until their suspension (see Figure 11).

Figure 11 Initializing Simulation

You can run simulation for an unspecified amount of time. For that choose Run from the Simulation menu. To advance a simulation by a specific time step, set the desired time step in the Simulation Step box located in the main toolbar (see Figure 12). Choose Run For from the Simulation menu or choose Run Until from the Simulation menu. Specify the desired time until a simulation should run and then click OK.

Figure 12 Simulation Step box

PAUSE/End Simulation

Waveform Viewer

Active-HDL offers two waveform viewers:

By default, the Accelerated Waveform Viewer is enabled and an *.asdb simulation database is created upon initialization of simulation. The Accelerated Waveform Viewer should be the pseered choice for designers working with large amounts of simulation data. It is optimized for large designs and long simulation runs.

The Standard Waveform Viewer/Editor is better suited for working with small designs, especially in the interactive mode. For example, it can show how the current simulation overwrites results from the previous simulation run and allows you to use hotkey stimulators.

Opening a new waveform file and adding signals

Figure 13 Adding Signals to Waveform Viewer

Saving the waveform file for off-line viewing

NOTE: Please stop the simulation before saving the waveform file.

Use the restart button to reinitialize the simulation without losing the signals in the waveform.

Saving the waveform file for reuse in successive simulations

The Waveform | Save to macro menu option or the File | Export menu command allow generating a macro (.do file) that can restore the view of the Waveform Viewer in your successive simulation runs and it contains a number of add wave or list commands for each signal found in the *.asdb file (see Figure 14).

Figure 14 Save to Macro

Running a macro file

Saved macro file can be used later to add the signals on the waveform for another simulation run. You can execute this macro in your script immediately after you initialize your simulation.


Within the tool

Go to menu Help | Product Help to learn more about Active-HDL.

Help on web

Go to to access the online database and other technical documents about Active-HDL.

Support Account

Register or use your Aldec support account at to open a support case or download the software.

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