File Management with Relative Paths in Active-HDL

File structure in Active-HDL

Every time you open a new design project, Active-HDL will automatically generate a design directory for you. It has the same name as your project name. Each design directory starts with three subdirectories: SRC, COMPILE, and LOG. The SRC subdirectory contains source files such as VHDL/Verilog source files, block diagram files, and state diagram source files. The COMPILE subdirectory contains the files that record compilation information for your design and HDL files generated from Block Diagram and State Diagram files. All log files such as log for your console are stored in the LOG subdirectory. Also, you can include files that you have stored elsewhere in your computer in your design project. You have two options for those files: either make local copies to your design directory, or just put a link to where you have physically stored those files. Figure 1 shows how you can specify if you want a local copy:

Figure 1: Make local copy checkbox in Add Files window

When local copy of the file was created, it was placed in the SRC subfolder of your current project folder. You can always refer to this subfolder using the $dsn system variable:


All your design files, no matter if it has a local copy or not, are shown in the Design Browser window. The hierarchy structure shown in the Design Browser is based on your design, not on how the files are physically stored on your computer.

Relative Paths for Linked File

If a design file does not have a local copy, it is a linked file. Linked files are shown in Design Browser window with a special Link icon (Figure 2):

Figure 2: Linked file icon in the Design Browser.

In an interactive way, you can compile linked files from the Design Browser window by right-clicking on the file and choosing the compile option. To compile linked files into your Active-HDL design using script command, you have following ways:

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