Today, System on Chip (SoC) designs can increasingly be found in applications for various fields spanning from entertainment through wearable electronics, health, automotive or even airborne and space industries. The approaching Internet of Things (IoT) era makes it obvious that the number of SoC applications will continue to increase in the coming years.
This reality imposes very high demands on design verification engineers that require productive methodologies to assure SoC have superior quality and are verified and taped-out on time. For this reason, FPGA prototyping and emulation are become more prevalent. Due to the size of the SoC, prototyping boards must contain multiple, large FPGA devices and be easily scalable. Selecting or designing the proper FPGA prototyping board, then later proper design partitioning are among the challenges many teams are facing.
From an ASIC design point of view, SoC is a paradigm shift from designs dedicated to a single function to complex multi-function systems. To keep pace with this trend the SoC projects rely on re-usable IP cores and architectures involving standard buses like AXI, AHB, Wishbone or OCP that are further integrated into Network-on-Chip components (NoC).
Such a modular design and use of standard buses makes it possible to verify every sub-system separately not only running simulations but also in emulation or prototyping. Later on, when it comes to SoC prototype integration, sub-systems are again used as the base structural units in design partitioning process.
Modular SoC designs require flexible and scalable prototyping solutions. Scalability is achieved with a modular design consisting of a backplane and base boards, such as HES-7 which was architected to allow for easy prototype implementation and flexible expansion. Using a non-proprietary backplane connector, HES-7 can easily expand prototype capacity up to 288 million ASIC gates. There are two base board models available within HES-7 line.
|HES-7 base prototyping boards|
|2 Virtex 7 2000 FPGA (up to 24M gates)||6 Virtex 7 2000 FPGA (up to 72M gates)|
The HES-7 platform is scalable due to ability to use base boards in a stand-alone mode as a fully featured prototyping bench with a PCIe host connector. Single board configurations are appropriate for smaller size SoC or to verify selected sub-systems. As the design grows, or when the time comes to verify complete SoC with all its sub-systems, the HES-7 can be scaled up with a backplane.
Developing a solidly reliable backplane design of prototyping boards containing high-density FPGAs is a complex task requiring months of development and testing. Traces in the backplane must be carefully routed to assure maximum transmission speed. Interconnections provided by the backplane should be well balanced to avoid inter-FPGA transmission bottlenecks that could limit the overall speed of the prototype.
Taking the HES7BPX4 backplane board as an example of balanced connectivity, the block diagram below illustrates connections between 8 FPGA parts in case of populating all 4 slots with the base board HES7VX4000BP.
This board design assures optimum connectivity for most SoC designs. Another approach is to match the board layout to SoC sub-systems connectivity, however this is uncommon as these boards could then only be used in one project.
Typically, SoC architecture suggests natural inter-partition borders that divide design across subsystems. It is also very common that different sub-systems can run at different clock ratios. This property can be used to drive each sub-system with clock generated locally and so achieve maximum prototype or emulation speed. With all above considerations, the SoC can be mapped to HES7BPX4 as shown below.
Benefits of using HES-7