The speed of the HDL simulation is the primary bottleneck of the design cycle when it comes to verification of ever growing ASIC designs. Limiting the number of simulation tests to meet requirements of tight schedules is alarming and raises doubt about the completeness of verification.
Newer methodologies like UVM or VMM automate the verification process with constrained random test generators but require much longer simulation times.
The remedy for ever increasing simulation times is using emulation techniques for simulation acceleration.
Simulation is accelerated by placing resource-hungry modules in the FPGA board while the simulation is controlled by the HDL simulator. This verification method combines benefits of HDL simulation (signal visibility) and emulation (speed). Moreover the acceleration will reuse simulation testbenches without compromising their functionality or verification methodology.
With HES-DVM™, simulation of multimillion gate count SoC designs can now be accelerated in excess of thousands times in comparison to pure HDL simulation. All possible verification environments are covered with two available signaling abstraction levels:
The current trend is to raise abstraction level in verification infrastructure from signal level to transaction level. The obvious benefits of this paradigm shift are:
HES-DVM keeps pace with this trend enabling use of emulation techniques for simulation acceleration with transaction level testbenches. The base of transaction level simulation acceleration is the Accellera organization’s Standard Co-Emulation Modeling Interface (SCE-MI) standard.
Supporting both Function and Macro Based versions of SCE-MI, the Design Verification Manager (DVM) in HES-DVM automatically compiles the DUT with transactors (Xtors) for emulation in FPGA prototyping boards such as HES-7™ or in-house developed boards. The testbench is entirely reused, so the emulator becomes a vehicle for simulation acceleration.
Emulation driven by a transaction level testbench runs thousands times faster than pure HDL simulation breaking the obstacle in efficient use of constrained random verification methodologies.
Comprehensive debugging features of HES-DVM allow using simulation acceleration even if design blocks are not ready to begin SoC integration.
Signal level acceleration mode is very flexible and allows accelerating either entire systems or only selected blocks at lower design hierarchy levels. It does not have any assumptions about the testbench type or verification methodology. Design Under Test (DUT) in the simulator is replaced with VHDL, Verilog or SystemC wrapper which is signal-level compatible with original module. The DUT is running in the emulator thus offloading the HDL Simulator significantly.
Aldec provides HES™ Co-simulation plug-in libraries compliant with PLI/VHPI standards, so simulation acceleration can be used with Aldec’s or any 3rd party HDL simulator.
The design compilation, setup and generation of DUT wrapper are fully automated with the Design Verification Manager (DVM) in HES-DVM.
Although the HDL designs are accelerated in the FPGA board, designers can still use the HDL simulator as the main debugging tool because all design output signals and debug probes are fed back to the simulator’s waveform viewer. This allows debugging of the design at silicon-level accuracy and faster simulation runs even at the early stage of the design cycle, leading to more discovered bugs and errors in a relatively much shorter time frame.