|Press Release||Aldec Delivers Complete Support for UVM 1.1, Enabling VMM and OVM Interoperability|
|Presentation||OVM/UVM for FPGAs: The End of Burn and Churn|
|Solution||UVM Transaction Debugging|
|Webinar||OVM and UVM - Building a SystemVerilog Testbench in Riviera-PRO|
Universal Verification Methodology (UVM) is an open source SystemVerilog library allowing creation of flexible, reusable verification components and assembling powerful test environments utilizing constrained random stimulus generation and functional coverage methodologies. UVM is a combined effort of designers and tool vendors, based on the successful OVM and VMM methodologies. Its main promise is to improve testbench reuse, make verification code more portable and create new market for universal, high-quality Verification IP (Intellectual Property).
Open Verification Methodology(OVM) is the library of objects and procedures for stimulus generation, data collection and control of verification process. Available in SystemVerilog and SystemC, OVM allows easy creation of directed or random test utilizing transaction-level communication and Functional Coverage. As the first SystemVerilog-based verification library available on multiple simulators, OVM contributed significantly to the development of its successor, Universal Verification Methodology.
Verification Methodology Manual(VMM) was the first successful and widely implemented set of practices for creation of reusable verification environments in SystemVerilog. Created by Synopsys, one of the strong proponents of SystemVerilog, VMM harnesses language features such as object-oriented programming, randomization, constraints, functional coverage to enable both novices and experts to create powerful verification environments. VMM contribution was an important factor in creation of UVM.