Open Source - VHDL Verification Methodology (OS-VVM) delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, providing advanced features to VHDL design engineers while enabling them to continue to develop using VHDL.

Aldec, in its continued commitment to provide continued support to the VHDL design community, has helped establish the OS-VVM Forum, where users are encouraged to work together to help grow the methodology. Visit www.osvvm.org for more information, to download documentation and software package, as well as to participate in future development.


Note: Aldec tools offer the advanced randomization and functional coverage capabilities provided by OS-VVM with a simple flip of the VHDL-2008 switch - no additional licenses are required.

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