CDC Verification CDC Verification Solution ALINT-PRO™ features a ALDEC_CDC rule plug-in that is focused on clock domain crossings analysis and handling of metastability issues in complex, modern multi-clock designs. Included CDC rules uncover critical problems during the RTL Design and Functional Verification stages, significantly cutting down time to market. THe CDC verification strategy is comprised of three key elements: static structural verification, design constraints setup, and dynamic functional verification. Static checks are implemented in the form of linting and performed in ALINT-PRO while dynamic verification is based on integration with Riviera-PRO™, Active-HDL™, or ModelSim® through automatically generated SystemVerilog or VHDL testbench. The testbench can be seamlessly integrated with an existing design and enables revealing metastability triggered issues during RTL simulation. ALINT-PRO is equipped with CDC Viewer designed to facilitate CDC issues analysis. It is capable of showing asynchronous clock domains with a distinct color in the Schematic Viewer, also displaying a detailed view of the detected clock domain elements, related clock and reset signals, grouping identified clock domain crossings and synchronizers to help user to understand whether the discovered asynchronous transfers are being properly handled. This enables high level design analysis in respect to the Clock Domains partitioning. Design Constraints Support Design constraints support is an essential element for proper clock domain verification. ALINT-PRO™ can read SDC files for design configuration and retrieve information relevant for linting. This includes: clock declarations and relations between them, input and output ports correlation to the clocks, etc. Without the constraints ALINT-PRO attempts to do it’s best to detect the structure of the clock, reset networks, I/O delays and CDC synchronization circuits automatically on its own based only on the netlist topology and predefined circuit patterns. The tool is capable of generating the initial draft of the SDC file for the use in subsequent design stages, such as timing-driven logic synthesis and static timing analysis.The generated SDC draft contains clocks declarations, including master and generated clocks, asynchronous clock groups and description of I/O delays for the top level ports relatively to the reading/writing clocks correspondingly. The exact clock frequencies and delay values cannot be extracted from the RTL, so default values are used, which should be adjusted later before using in the subsequent design tools. Mixing partially specified SDC input and automatic detection is allowed. Both methods complement each other, and SDC can often be used to direct the automatic detection into a right direction, which is hard to avoid in some advanced cases, especially in ASIC designs having complex custom clock gating, multiplexing and scan-enable circuitry.. ALINT-PRO offers custom extension to design constraints: Aldec Design Constraints (ADC). These constraints are divided into two groups: Block-level design constraints – used for describing modules, which cannot be directly synthesized: FPGA vendor primitive, behavioral models, encrypted IP. It is also possible to describe custom synchronizer to validate its correct usage in the design Chip-level design constraints – used for describing reset networks and retrieving additional information from the netlist ALINT-PRO provides pre-packaged, up-to-date accurate timing annotations (block-level constraints) for the most relevant Xilinx, Altera,Microsemi and Lattice FPGA libraries, including input and output delays relative to clock pins, and multi-mode primitives having timing behavior dependent on the values of particular generics. This dramatically reduces the amount of false CDC positives and uncovers previously invisible clock domain crossing paths. Writing custom block-level constraints is a must for the designs instantiating complex multi-clock IP-blocks (in ex., encrypted cores) and other types of black boxes. The user needs to explicitly declare clock and asynchronous control pins, as well as to express the relation between non-control I/O pins and the assumed clocks. Without clear timing abstraction associated with the black-box, ALINT-PRO makes pessimistic assumptions regarding the possible clock domain crossings within the block, and may generate many false positive messages. Block-level design constraints can also be used to improve the performance of CDC analysis using hierarchical approach. If a large design block was already verified against the internal CDC issues, it makes sense to replace it with a black-box and block-level design constraints model, as new CDC violations related to the verified block may only appear at it’s I/O border. Static Verification ALINT-PRO features a set of rules (ALDEC_CDC rule plug-in), which can be statically verified. These rules consist of two sections: constraint rules (clocks,resets, and I/O delay analysis) and CDC rules (synchronizer’s structure analysis). A Phased-Based CDC Flow can be utilized to facilitate running the rules in a recommended predefined order that minimizes the potential number of verification reruns until the design reaches a CDC-clean state. Clock and reset networks verification is performed prior CDC checks to ensure proper clock domains extraction. The CDC rules verify crossings between asynchronous clock domains. Crossings are verified against having combinational logic, convergence or divergence. It is also checked, that a valid synchronizer is present on the crossing. For the asynchronous resets de-assertion is verified to be synchronous with the proper clock. Finally, the uncovered synchronizers are checked against combinational or sequential re-convergence, possibly very deep in the target domain. Dynamic Verification Structural checks can verify that proper synchronizer is present in on the crossing, however to ensure there are no CDC bugs, the communication protocol should be verified. ALINT-PRO can generate SystemVerilog, pure VHDL, and VHDL with PSL testbench to enhance RTL simulation with additional checks. It contains the following elements: Metastability Emulation – behavioral SystemVerilog or VHDL code, which inserts random delay on crossings between asynchronous clock domains. This allows revealing such issues as missed pulse or data incoherence during RTL simulation. Assertions – assertions are generated for synchronized crossings to ensure proper usage of the synchronizers. This includes checks for data stability and proper capturing data sent over clock domain boundaries. Coverage – allows validating user’s testbench to trigger data transfers on the synchronized crossings and that random delay, inserted due to metastability emulation, has actually occurred during the simulation. Generated testbench doesn’t contain stimulus and cannot be used for simulation without design’s original testbench.