HDL development and verification under DO-254 guidelines is a rigorous undertaking, and requires special features and capabilities from HDL design and simulation tools. Active-HDL™ or Riviera-PRO™ provides features for graphical design creation, verification, management and documentation facilitating a flexible and seamless design and verification platform.
The Block Diagram Editor is a tool for graphical entry of VHDL, Verilog and EDIF designs. If the HDL design is in large part structural, it may be easier to enter its description graphically as a block diagram, rather than typing hundreds of source code lines.
The State Diagram Editor is a tool designed for the graphical editing of state diagrams of synchronous and asynchronous machines. Drawing a state diagram is an alternative approach to the modeling of a sequential device. Instead of writing the HDL code manually, the designer can enter the description of a logic block as a graphical state diagram.
The code to graphics converter is a tool designed for automatic translation of VHDL or Verilog source code into block and state diagrams. It analyzes VHDL, Verilog, or EDIF source files and generates one or more block diagram files depending on the number of design entities, modules, or cells found in the analyzed file. The resulting block diagram files can be automatically attached to a design.
Best level of support for VHDL 2008 language standards. The latest standard, IEEE Std 1076-2008 (better known as VHDL 2008), brings long-awaited improvements and many new, nice features: all popular types defined in one standard, improved and extended operators, better "if" and "case" statements, combinatorial process(all), improved "if..generate" and new "case..generate", expressions in port maps, reading from outputs, external names, source code encryption, assertions, VHPI, etc. For better compatibility, simulators can be switched to VHDL 2002 or 93 modes if needed. For greater convenience, the simulator is equipped with options that allow optimization of simulations for maximal speed or extensive debugging while strictly adhering to IEEE Standards.
This tool offers a number of features to effectively debug errors and verify the behavior of the design. The interactive debugging features included are HDL Syntax Checking, Source Code Tracing (Trace Into, Trace Over, Trace Out, Trace Over Transition), Breakpoints Insertion, Block Diagram Graphical Debugging and State Machine Graphical Debugging. Multiple windows to view simulation results are also available including List (Delta) Viewer, Watch Window, Processes Window, Waveform Viewer, Dataflow Window and Call Stack Window.
Post Simulation Debug is a very useful feature that allows simulation a project in the "off-line" mode (without a connection to the simulator). The engineer can perform only one regular simulation to collect the post-simulation data and then analyze the design as many times as needed in the post-simulation mode. Moreover, the engineer can share results of the simulation with others as well as use post-simulation files prepared by someone else on a different computer.
A tool that allows designers to explore the connectivity of an active design and analyze dataflow among instances, concurrent statements, signals, nets, and registers during simulation. The tool consists of multiple graphical views: hierarchical, flat, or gray dataflow diagram that is especially helpful while tracing events propagating through the entire project and identifying those that may be potential sources of unexpected output values.
Waveform Viewer is a tool designed to display simulation results in the form of graphical waveforms. During simulation, the simulation kernel outputs waveforms for previously selected signals, static variables (shared variables and variables defined in processes), nets, and registers in the Waveform Viewer/Editor window. Waveforms can be re-applied as test vectors to signals and nets during subsequent simulation runs. Waveforms can be printed or exported into a PDF or HTML to be used for documentation.
Unknown and uninitialized values ("x", "w", -, etc.) can be a source of an unexpected behavior on output ports of a tested entity/module. This tool is a command-line utility that allows detection and reporting of unknown values when they first appear and before they are propagated through a design. It allows stopping the simulation when an unknown value is assigned to any of monitored signals. Corresponding messages about unexpected values, signals and the time when those values were detected are also displayed in the console window.
Assertions can be used both for detecting errors in a design and for verifying and describing complex sequences of events. Assertions can be used to verify requirements. Assertions can be encapsulated in reusable units with parameterized verification rules, providing the possibility to create independent checkers, specialized for user-defined or universal protocols frequently used in designs.
Code Coverage is a debugging tool that allows users to check how satisfactory the source code has been developed. Code Coverage checks how much HDL statements from a testbench are executed during the simulation, and how much elements in the HDL design have been verified. Code Coverage is also used to support Elemental Analysis, an advanced verification approach described in RTCA/DO-254 Appendix B 3.3.1.
Toggle Coverage is a program that measures a design activity within terms of changes of signal logic values. Toggle Coverage creates a report that provides information: whether monitored signals were initialized, whether monitored signals experienced rising and/or falling edges, and the number of rising and falling edges during the simulation session. The report helps verify the quality of stimulus and locate non-active structures of the design. Signals that were not initialized during the simulation or are not exercised properly by the testbench can be easily identified.
Path Coverage is a debugging tool that collects information about the program execution and analyzes whether all combinations of program sequences (program paths) are verified by a testbench. A program path is a sequence of statement executions performed in a particular order. The tool also collects information about the order of how the consecutive statements are executed, the branches that are examined, and how logical conditions evaluated during simulation.
Source Revision Control allows operating on subsequent versions and revisions of design source files directly from the HDL simulator environment. In such an environment, it is possible to track the changes in a design and view differences between subsequent versions of files. The Source Revision Control system also makes team work easier as it allows a group of designers to work on the same project. Once the files are archived in a repository, they are available to other team members. Additionally, all changes that have been made to any file are saved with a full history, so you can recover any version of any file at any time. Members of your group can see the latest version of any project, make changes, and save a new version in the Source Revision Control system database.
Design documentation for DO-254 certification is a necessity. This tool consists of powerful documentation features allowing the engineer to create a textual or graphical representation of the workspace or design in HTML or PDF format. All design elements such as design files, waveforms, block diagrams and attached documents can be exported to HTML or PDF documents which can be controlled by various options in the wizard. The resulting documents always preserve the hierarchy of the design which provides easy navigation in complex designs. Export to vector graphics capability maintains the high resolution of schematic files in the generated document.
Active-HDL's Design Flow Manager provides seamless interfaces with 3rd party synthesis and P&R tools and facilitating a unique platform that can be used throughout the FPGA design flow.