In compliance with RTCA/DO-254 and FAA AC 20-152, verification of FPGA/PLD level requirements must be done to ensure completeness of testing. DO-254/CTS™ is a fully customized hardware that provides FPGA level verification for the target device. The target FPGA device is isolated in a custom board which is stimulated by the simulation testbench running at full speed allowing a comprehensive and automated functional test for all FPGA level requirements in a single environment.
This tool consists of a custom hardware that contains the specific family/package or part number of the FPGA/PLD device from vendors such as Altera, Microsemi (Actel) and Xilinx. It allows streaming of test vectors through the FPGA inputs at the required operational speed using real clocks in excess of 250 MHz. If the required simulation time is 500ms, then hardware testing completes within 500ms. Additional features to vary the frequency and voltage to +-10% can also be used for robustness.
Development of test vectors for hardware testing for an average Level A/B design normally takes 6-12 months manual engineering time. This tool is equipped with a utility that converts the testbench within minutes into test vectors to be used for hardware testing. This ensures the same requirements that are verified in the RTL simulation are verified again for in-hardware verification. Therefore, FPGA level requirements are preserved and verified from RTL simulation to hardware testing per RTCA/DO-254 specification section 6.2. No changes to the testbench are necessary.
Traditionally, multiple sets of testing environment must be created to verify multiple sets of FPGA requirements, and this usually entails manual connections/bypasses of wires and cables which are prone to errors and bugs. One of the primary goals of this tool is to prevent such cases. This tool consists of custom hardware (PCIe interface) and software providing a single-environment to test all FPGA level requirements.
This tool is a "push-button" automated in-hardware testing environment to test all FPGA level requirements. It is equipped with a utility to automatically compare RTL simulation results with hardware testing results. The utility displays either a PASS or FAIL message in which results can be further investigated using a standard waveform viewer.
The capabilities for capturing/recording and visualization of hardware testing results using Logic Analyzers and Digital Oscilloscopes are limited. This tool allows capturing and visualization of results using the simulator’s standard waveform viewer, providing storage for waveform files of up to 16TB and capturing of results immediately after simulation. Comparison between RTL simulation and hardware testing results is also possible.
This tool can be used with any 3rd party HDL Simulator, Synthesis and P&R tools.