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Driving Innovation in Image Sensors and High Speed Analog/Mixed-Signal Design

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Integrating SystemVerilog and SCE-MI for Faster Emulation Speed
In Memory of Jerry Kaczynski
Why Randomize?
Following the Roadmap to Successful Traceability
SCE-MI for SoC Verification
Verilog-AMS & Multi-Level Simulation
The WHAT is mandatory but the HOW is entirely optional
90’s Kid Active-HDL Celebrates Sweet 16
The Magic of CyberWorkBench
HW Designers: Brush up on your SV with Online Training
ASIC/FPGA High Level Synthesis Solution from NEC
Leverage Hardware Acceleration for Faster Simulation
Working Smarter not Harder
Legacy Schematic Designs Giving you a Headache?
Riviera-PRO 2013.06 Enables Class Hierarchy Visualization
Aldec and Xilinx, Partnered for Success
DO-254: Insights from a DER
Wait….Did you say HDL Editor?
Demystifying Traceability
Back from DAC
'Wireless Algorithm Validation’ with Aldec and Agilent
Industry’s first Requirements Lifecycle Management for Safety-critical FPGAs and ASICs
High Performance SoC’s Pushing the Limit of Prototyping Boards
Active-HDL Tool Trainings Help Engineers Get up to Speed Quickly
UVM Webinar for Hardware Designers
Automatically Perform Repetitive Tasks with Mouse Strokes
Improve Productivity with User-Defined Design Management
EE Journal Chalk Talk “Integrated Design Environment for FPGA”
"Best of 2012" Top Webinars
Now Available - Verification White Papers
Increased Debug Capability with Hardware Emulation
Time-Saving, Hardware-assisted Verification
Fastest Co-Simulation Interfaces
Shaping the Future of ASIC/FPGA DSP Design Flow
Fast Track™ to SystemVerilog for Verilog Users
ARM Cortex SoC Prototyping Platform
Aldec in the Classroom
Register for Aldec Technical Sessions & Demos at DAC 2013
HES-7™ 7-Series FPGA Programming
Building an Efficient Clock Network
Those Pesky SystemVerilog Interfaces...
Aldec Adds HES-7 Prototyping Platform
'Fast Track to UVM' Interactive Online Training
2012: Emulation's Big Year
Best Design Practices
Controlling Riviera-PRO from MATLAB®
Robustness Testing for DO-254 Designs
Interoperability of Project Tasks
Camouflage for Your HDL Code
Simplify your FPGA Verification
Xilinx Opens Their IP for Simulation with Aldec Flow
Using Plots for HDL Debugging
Elemental Analysis of Requirements-based Verification
Aldec and NEC reveal HLS shortcut at upcoming SoC Conference
Biggest Hits and Trends from ARM TechCon
Do you really need FPGA Design Management?
Does DO-254/CTS™ Support FPGAs with Serial High-speed I/Os?
Effective Communication is Key in Relationships… and ESL Design!
HES-DVM™ 2013.11 Delivers Increased Speed and Debugging
It’s no accident that Aldec offers the best VHDL-2008 support
Much has changed in the last 30 years
Still managing FPGA requirements with Word and Excel?
Why Digital Design Students choose Active-HDL™
For DO-254 Compliance, Hardware Flies Not Simulations
Visualizing UVM Environments: Debug Features Deliver a Clearer View
Simulate Smarter than a Secret Agent
See the Future with Impact Analysis
Averting Clock-Domain Crossing issues in FPGA Design
The 80s music at DAC was my idea. You’re welcome.
DO-254/CTS™ solves Elbit’s major challenges
The Future of EDA?
SVUnit Adds Support for Aldec Riviera-PRO Users
Stress-Relief for Requirements-Based Verification
FPGA-Based Prototyping Q&A: 100 Million Gates and Beyond
Want to be a Verification Engineer? Practice. Practice. Practice.
Averting CDC Roadblocks in FPGA Design
How HES™ Technology Solved Problems for These Users
Looking for Practical Holiday Gift Ideas?
Spec-TRACER now directly integrated with IBM DOORS
Last call from Engineer Santa. Survey & daily drawings end Dec 12.
Scaling the “Internet of Things”
Webinars, YouTube, Articles... What’s your preference?
Transitioning to Advanced Verification Techniques for FPGAs – Catch-22?
It’s Here! ALINT-PRO-CDC™ for CDC Verification
What inspired you to become an engineer?
Xilinx Tcl Store Integrates Aldec Simulators with Vivado IDE
Are Metastability Monsters Lurking Beneath the Surface?
Save hours of Place & Route time… in seconds
How to Properly Verify Encrypted IP
How can Verification IPs Help the SoC Testing Process?
So, what does a vendor-independent simulator look like?
Putting the “Automation” back into EDA
FPGAs Cross Scale Threshold to Enable True FPGA-based Verification
DO-254 Book: Airborne Electronic Hardware Design Assurance
Extend Vivado Capabilities with Help From the Tcl Store
Code Coverage – Can we get a little help here?
A Winning HDL Design Strategy
Developing high-reliability FPGAs for DO-254
Helping FPGA Designers get started with UVM
The Science of Verification
‘Don’t Be Afraid of UVM’ Webinar on YouTube
The Problems with CDCs
UVM Really is Everywhere
A Comprehensive RTL Verification Solution for VHDL
UVM Spells Relief
Verifying Large FPGAs Isn't Easy
Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs!
UVM It’s Organized and Systematic
Why I see C in SCE-MI
Acceleration-Ready UVM
UVM Register Layer: The Structure
Aldec Verification Tools Implement the ASIC Verification Flow
To Emulate or Prototype?
The hardest part of DO-254 is
Vegetarian Dining in Austin - DAC 2016
The UVM Configuration Database
Introduction to AXI Protocol
It’s Time to Get Your University in Sync with Zynq
Aldec Engineers: Taking Action and Giving Back as a Team
FPGAs Accelerating IoT Gateway and Infrastructure Tiers
Leveraging the Power of VDMA Engines for Computer Vision Apps with TySOM™ - Part 1
Leveraging the Power of VDMA Engines for Computer Vision Apps with TySOM™ - Part 2
Beer, Cars, and Verification
FPGA VHDL Verification
An Easier Path to Faster C with FPGAs
Key Components of Effective RTL Linting and CDC Verification
Software Driven Test of FPGA Prototype
Aldec Springs Into Action
FPGAs in an SoC World
Emulation on the Cloud
Austin's Best Vegetarian Restaurants: The Quest Continues
VHDL-2017: Some of My Favorite Things
Traceability Matrices: Headache or Real Value
Accelerating Simulation of Vivado Designs with HES
Introduction to Zynq Architecture
Demystifying AXI Interconnection for Zynq SoC FPGA
Don’t be a Slave to the Documentation
Synthesis of Energy-Efficient FSMs Implemented in PLD Circuits
Understanding the inner workings of UVM
Zynq-based Embedded Development Kit for University Programs
Code Coverage in HDL Editor? Now That’s a Nice Feature
Emulation in FPGA
Plots: A New Way To Analyze Data
Partition your Design for FPGA Prototyping
How to Design the New Generation of Reprogrammable Router/Switch Using Zynq FPGA
Understanding the inner workings of UVM - Part 2
How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1
Trace Your Assertions
Unit Linting: An easy way to prevent code review issues
SystemVerilog Functional Coverage in a Nutshell
Do I really need a commercial simulator?
Understanding the inner workings of UVM - Part 3
FPGA vs GPU for Machine Learning Applications: Which one is better?
Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench
The Race to Zero Latency for High Frequency Trading
Problems Accessing Registers? See how UVM RAL can help
HW/SW Co-Simulation for SoC FPGA designs
The Power of PCIe in Performance-based FPGA World
What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA?
No Risk No Fun
35-years-old, and still on point