Take a look on how to make use of the UVM Toolbox available in Riviera-PRO for debugging designs and making the most of your verification environment. Use the UVM Viewer, UVM Hierarchy, and UVM Configuration windows to represent UVM architecture and their TLM connections to improve the perspective of the architecture and dataflow.

The UVM Register Generator is used to create Register Model files to incorporate into a UVM environment to use the Register Abstraction Layer of UVM. Automatically generating models for the RAL is particularly time saving, considering modern designs can consist of thousands of registers, and coding those by hand would be a long and tedious task, while still being a crucial aspect of the verification of the design.

Riviera-PRO provides the Transaction Level Modeling (TLM) interfaces for use with VHDL, Verilog/SystemVerilog, and SystemC industry standard languages. The TLM interfaces have been also implemented in the SystemVerilog UVM/OVM and SystemC Verification (SCV) libraries delivered with Riviera-PRO.

Visualizing the hierarchy and the connectivity of an active design and analyzing the dataflow among the instances, concurrent statements, nets and registers. Monitoring the design for undesired and unknown values using Xtrace. Combining Xtrace with Advanced dataflow for quick exploration of the drivers of unknown values.

In this video, Application Engineer Henry Chan, explains how emulation can help accelerate UVM-based testbenches and explores the benefits of emulation/acceleration over traditional simulation tools. A cursory overview of the Accellera SCE-MI standard as well as some necessary testbench modifications for emulation/acceleration are presented.

Jenkins is an open source automation server allowing for continuous integration of HDL design in a collaborative environment. In collaboration with Riviera-PRO's batch mode, Jenkins can periodically poll shared repositories belonging to a design team and execute build orders on the detection of source code modifications.