VIP/IP Products

DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmission via cable networks. It complements the existing standards DVB-S2 and DVB-T2 for satellite and terrestrial communication and offers a capacityapproaching coding scheme. The Creonic DVB-C2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder). It furthermore includes additional signal processing before and after forward error correction (soft-decision demapping, deinterleaving, descrambling).

DVB-RCS (Digital Video Broadcast - Interaction channel for satellite distribution systems) is an established ETSI standard for digital data transmission via satellites. It uses a 8-state double-binary turbo decoder that has an excellent error correction performance. This outstanding performance of the DVB-RCS turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digital data transmission via satellites. It uses a new 16-state doublebinary turbo decoder that significantly outperforms its dated 8-state counterpart of DVB-RCS. DVB-RCS2 is the first standard to adopt these highest performance turbo codes. New modulation schemes (8-PSK and 16-QAM) help to increase spectral efficiency even further. The outstanding error correction performance of the DVB-RCS2 turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first standard of the second generation DVB standards (DVB-S2/-T2/-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).

GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes for the first time. The same burst modes and LDPC codes are also in GMR Release 3 (GMR-3G). The Creonic GMR LDPC decoder IP core is a field-proven solution.

The WiFi family of standards (IEEE 802.11) is used for Wireless Local Area Networks (WLANs). Its first version from 1997 has been extended by many amandments such as IEEE 802.11n-2009 (now part of IEEE 802.11-2012). This amendment was developed in particular for high throughputs of 600 Mbit/s on the air interface. The standard uses convolutional codes for forward error correction as minimum requirement. LDPC codes are optional but because of their superiority over convolutional codes they are widely used today.

The Creonic IEEE 802.11 LDPC decoder is a high performance implementation for WLAN and further applications and supports all LDPC codes as defined by the standard.

The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN). Task group 3 of the working group focuses on high data rates within WPAN. The task group 3c defined a new millimeter-wave-based alternative physical layer (PHY) for the IEEE 802.15.3-2003 standard. This standard (IEEE 802.15.3c-2009) operates at 60 GHz and offers data rates of multiple Gbit/s for applications such as high speed internet access or streaming content download. The task group adopted LDPC codes for these high data rate modes within the single carrier (SC) mode and the high speed interface (HSI) mode.

The Creonic IEEE 802.15.3c LDPC Decoder IP supports all LDPC codes with a codeword size of 672 bits as defined by the standard.

MIMO (Multiple Input Multiple Output) techniques are being used more and more in recent and upcoming standards since they drastically outperform traditional SISO (Single Input Single Output) techniques in terms of maximum throughput and range. This gain results from an increased spectral efficiency, lowering the overall system costs.

A Minimum Mean Square Error (MMSE) MIMO detector is an integral part of a MIMO receiver. The Creonic MMSE detector offers high throughputs even on low-cost FPGAs and convinces with a low implementation complexity at the same time. Its flexibility at design-time and run-time makes it the ideal fit for all kinds of MIMO applications.

The WiMedia UWB standard was developed by the Wi-Media Alliance. Version 1.5 of the standard introduces high payload throughputs of up to 1 Gbit/s for short range communication. LDPC codes have been adopted for these high data rate modes, while convolutional codes are used for the low data rate modes. The Creonic WiMedia 1.5 LDPC Encoder and Decoder IP core supports all LDPC coding schemes as defined by the standard.

Serial Front Panel Data Port is an industry standard, low-overhead, low-latency, high speed serial communications protocol. sFPDP is ideal for use in applications such as high-speed communication system backplanes, high-bandwidth remote sensor systems, signal processing, data recording, and high-bandwidth video systems. The simple and lightweight nature of the protocol makes it an attractive choice for replacement of parallel bus interconnects using serial transceiver technology. sFPDP can be used in point-topoint or loop topologies, uni-directional or bidirectional links, and easily supports different types of data with efficient and flexible data framing options.

The Northwest Logic AXI DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems.

The CSI-2 Controller Core V2 is Northwest Logic’s second generation CSI-2 controller core. It is further optimized for high performance, low power and small size.

The Northwest Logic DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems.

The DSI-2 Controller Core is Northwest Logic’s second generation DSI controller core. It is further optimized for high performance, low power and small size.

The DSI Controller Core is part of Northwest Logic’s MIPI Solution. This solution is designed to achieve maximum MIPI throughput while being easy to use.

The Expresso 3.0 Core is part of Northwest Logic’s PCI Express Solution. This solution is designed to achieve maximum PCI Express throughput while being easy to use.

The Expresso 4.0 Core is part of Northwest Logic’s PCI Express Solution. This solution is designed to achieve maximum PCI Express throughput while being easy to use.

The Northwest Logic Expresso DMA Bridge Core provides high-performance DMA and/or bridging between PCI Express and AXI for both Endpoint and Root Port applications.

The Northwest Logic Expresso DMA Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems.

Highly capable loss-less data compression and expansion cores capable of >1Gbps throughputs in FPGA without any requirement for external RAM.

Easy to use and highly integrated AES-CCM cores offering combined encryption and data authentication in a single engine.  Compliant with standards like 802.11, 802.15, 802.16, Zigbee, IEEE1619.1.

Easy to use and highly integrated AES-GCM cores offering combined encryption and data authentication in a single engine.  Compliant with standards like IPsec,

Easy to use and highly integrated AES Key Unwrap core, implementing the NIST AES Key Unwrap algorithm and AESKW mode of ANS X9.102.

Easy to use and highly integrated AES Key Wrap core, implementing the NIST AES Key Wrap algorithm and AESKW mode of ANS X9.102.

Cryptographic Pseudo Random Number Generator which implements ANSI X9.17 and X9.31 PRNGs based on either Triple-DES or AES encryption algorithms.

Easy to use block cipher core which implements DES and Triple-DES encryption and decryption to NIST FIPS publication 46-3.

Easy to use CSA core implements ETSI specified DVB Common Scrambling Algorithm which is ideal for use in BISS-E and BISS Mode-1 Digital Satellite News Gathering applications.

Low latency, high data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Easy to use Fast Hashing cores supporting the MD5, SHA-1, SHA-256, SHA-384 and SHA-512 hashing algorithms, aimed at high data rate applications.

Easy to use core which implements the Z = Y^E mod M, the Modular Exponentiation function commonly used in Public-Key Cryptography and ideal for hardware acceleration of RSA, Diffie-Hellman and DSA.

Super compact multi-mode Hashing core supporting the MD5, SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 hashing algorithms, each with optional HMAC, aimed at low rate applications.

Compact, mid data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Ultra low area, low data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Aldec 1-Wire Slave transactor provides capability to communicate over 1-Wire bus. It consist of fully synthesizable hardware part written in Verilog and software part written in C and SystemVerilog with API in SystemVerilog. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec AMBA High-performance Bus (AHB) transactor provides communication and monitoring capabilities with AHB devices (master and slave). It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec AMBA High-performance Bus (AHB) transactor provides communication and monitoring capabilities with AHB devices (master and slave). It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modeling Interface (SCE-MI) using macro based message passing use model

Aldec AMBA Advanced eXtensible Interface (AXI) transactor provides communication and monitoring capabilities with AXI devices (master and slave). It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec AMBA Advanced eXtensible Interface (AXI) transactor provides communication and monitoring capabilities with AXI devices (master and slave). It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

CSIX-L1 is a Common Switch Interface, for transferring information between switching fabric and traffic
managers (network processors).
The Aldec CSIX transactor provides capability to communicate over CSIX networking interface.
It consists of:
- fully synthesizable hardware part written in Verilog
- software part written in C and SystemVerilog
- Low Level API in SystemVerilog (giving full control, e.g. of flow control)
- High Level API in SytemVerilog (taking care of flow control)
Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI)

The Aldec Ethernet transactor provides capability to communicate over Ethernet networking interfaces:
- 1000 Mb/s (Gigabit Ethernet)
- 100 Mb/s (Fast Ethernet)
- 10 Mb/s
It consists of:
- fully synthesizable hardware part written in Verilog
- software part written in C and SystemVerilog
- API in SystemVerilog
Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI)

The Aldec Ethernet speed adapter provides capability to connect real-speed (up to 1000 Mbit/s) Ethernet interface to Ethernet DUT in Aldec emulator. Speed adapter handles synchronization between two domains (fast/real and slow/emulator) and manages protocol-specific flow control.

Aldec Inter-Integrated circuit (I 2C)  transactor provides capability to communicate over I 2C bus. It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec Inter-IC Sound (I2S) transactor provides capability to communicate over I2S bus. The I2S transactor uses one channel but combines both transmitter and receiver functions. Communication between an HDL model with a C model is provided by Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec IEEE 1 149.1 Standard Test Access Port and Boundary-Scan Architecture (Joint Test Action Group JTAG )  transactor provides capability to communicate over JTAG interface. It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec Tensilica JTAG transactor provides capability to connect software debugger (e.g. gdb or eclipse-based) to Tensilica CPU, without physical JTAG cable. It consist of fully synthesizable hardware part written in SystemVerilog and software library for Tensilica XOCD. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec OCP (Open Core Protocol) version 2.1 provides capability to communicate over OCP bus as master and slave. It consists of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Communication between HDL and C model is provided by Standard-CoEmulation Modelling Interface (SCE-MI)

Aldec PCI Express transactor provides communication capabilities with PCIe devices. It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI).

The Aldec PCI Express speed adapter provides capability to connect real-speed PCIE device to PCIe DUT in Aldec emulator. Speed adapter handles synchronization between two domains (fast/real and slow/emulator) and manages protocol-specific flow control.

ALDEC SPI 4.2 transactor provides communication with Link Layers devices with SPI 4.2 interface. It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard CoEmulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec TLM2SCEMI_AHB gives ability to connect Virtual Platform with AMBA AHB-based SoC in emulator. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec TLM2SCEMI_AXI gives ability to connect Virtual Platform with AMBA AXI-based SoC in emulator. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec UART transactor provides capability for serial communication with devices like CPU. It consists of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Communication between HDL and C model is provided by Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec Universal Serial Bus device transactor provides capability to communicate over USB2.0 bus. It consist of fully synthesizable hardware part written in SystemVerilog and software part written in C++ with C API. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing

The Aldec USB speed adapter provides capability to connect real-speed USB device to USB DUT in Aldec emulator. Speed adapter handles synchronization between two domains (fast/real and slow/emulator) and manages protocol-specific flow control.

Aldec WISHBONE Master Transactor provides capability to communicate over WISHBONE bus in Classic Mode. It consists of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Communication between HDL and C model is provided by Standard Co-Emulation Modelling Interface (SCE-MI)