HES-US-1320 Prototyping and Emulation Main Board

Product Description

Capacity

Aldec’s large capacity board with three XCVU440 logic modules is targeted to high speed physical prototyping and emulation of ASIC and SoC designs. The board provides estimated capacity of 79 Million gates and is easily extendable via backplane and daughter card non-proprietary connectors (BPX & FMC). Each UltraScale FPGA module is connected with DDR4 SO-DIMM to support up to 48 GB aggregated memory. Larger capacity of 316 Million gates can be achieved with four HES-US-1320 boards connected in the backplane board HES7BPX4. Highest I/O count packages of UltraScale devices and proper on-board traces routing assure reliable LVDS and GTH transfers up to the device inherent limits.

Clocking

Very precisely designed clocking block provides 5 length aligned global clock lines routed to each FPGA device. It also provides multiple configuration options due to integrating different oscillators, programmable clock synthesizers and crosspoint switch multiplexers. The global clock network can be also driven from external sources via dedicated SMA connectors as well as from backplane and daughter card sockets. The global clock network is based on LVDS signalling to assure high level of signals integrity and immunity to distractions. Complementary to global clocks there are separate clock oscillators dedicated to GTH links and DDR memories.

Hosting & Interfaces

The board configuration and monitoring controller is preloaded in a dedicated FPGA (Spartan-6) and provides USB based management interface that is used by Hes.Asic.Proto board configuration and management software available on Linux and Windows host PC. Additional Virtex-7 FPGA can be used as a host bridge with standard interfaces like PCIe x8 Gen3, USB 3.0, QSFP+ and SATA. Ready to use, PCIe host controller is preloaded in Virtex-7 FPGA and the corresponding HES PCIe driver is included. Usage of this host controller is facilitated due to Proto-AXI interface module IP that is based on AMBA AXI standard and accompanying high abstraction level C++ API.

Besides physical prototyping this board can be reused for HES emulation applications like simulation acceleration or co-emulation with virtual models.

BLOCK DIAGRAM

Essential Features

FPGA & Capacity

  • Main FPGA: 3x Virtex UltraScale XCVU440 (FLGA2892 - 1456 I/O, 48 GTH)
    • ASIC Gates estimated for 60% of FPGA utilization
      • 79 Million Gates single board
      • 316 Million Gates with four boards in a backplane
  • Host FPGA: Virtex-7 XC7VX690T (FFG1926)
  • Debug FPGA: Kintex-7 XC7K325T (FFG900)

Flexible Clocking

  • Flexible global clock network connected to each UltraScale and Virtex-7 FPGA
    • 5 global, low-skew, length aligned clock lines with fanout buffers
    • Configurable with PLLs & Crosspoint switch muxes.
      • Precision any-frequency clock synthesizer (Si5326)
      • LVDS crosspoint switch (DS10CP154A)
    • On-board LVDS clock sources
      • Oscillators: 192, 250, 300, 400, 500 MHz
    • External clock sources
      • 5 clocks from dedicated FMC connector
      • 4 clocks from backplane connector
      • 6 clocks from SMA connectors
      • 1 feedback clock line from each UltraScale FPGA (only in rev2)
  • Global reference clock connected to all FPGAs (fixed at 200MHz)
  • GTH reference clocks (UltraScale and Virtex-7)
    • Dedicated GTH oscillators (fixed at 200 or 156.25 MHz)
    • External from SMA connectors
  • Separate reference oscillators for each DDR (fixed at 200MHz)
  • 124 global clock I/O of all UltraScale FPGAs available on connectors
    • 68 DIFF clock lines from backplane connector
    • 56 DIFF clock lines from FMC daughter card connectors

Connectivity & Expandability

  • Full size BPX backplane connector
    • High speed (25 Gbps) connectors: MOLEX 76150 series
    • Backplane to UltraScale aggregated connections
      • 720 I/O (360 DIFF) - standard GPIO optimized for LVDS & TDM
      • 23 GTH - high speed serial I/O
      • 96 HR I/O (48 DIFF) - high voltage range I/O up to 3.3V
  • Daughter card connectors (FMC-HPC)
    • Standard FPGA Mezzanine Card connectors
      • Compliant with ANSI/VITA 57.1 FMC Standard
      • 4 FMC-HPC sockets connected to UltraScale FPGAs
    • FMC to UltraScale aggregated connections
      • 640 I/O (320 DIFF) - standard GPIO optimized for LVDS
      • 32 GTH - high speed serial I/O
  • Inter-FPGA connections
    • UltraScale interconnections
      • 710 I/O (334 DIFF) - standard GPIO optimized for LVDS & TDM
      • 31 GTH - high speed serial I/O
    • UltraScale to Virtex-7 host FPGA connections
      • 286 I/O (137 DIFF) - standard GPIO optimized for LVDS
      • 27 GTH high speed serial I/O
    • 89 I/O common/debug bus
    • 3 common lines
  • GPIO & Misc
    • Goldpin connectors
      • 80 I/O (40 DIFF) standard GPIO
      • 40 HR I/O (20 DIFF) - high voltage range I/O
    • 40 LEDs
    • 20 switches

Memory Resources

  • Up to 48 GB of DDR4
    • 6 DDR4 SO-DIMM slots
    • 2 slots and up to 16 GB per FPGA
  • Memories connected to Virtex-7
    • 1 DDR3 SO-DIMM slot
    • SPI Flash, NAND Flash
  • Micro-SD slot for memory to store FPGA configuration bit-files

Interfaces & Hosting

  • Host interfaces at Virtex-7
    • Two independent PCIe ports
      • Fixed PCIe x8 gen3
      • Configurable PCIe x16 / x8 gen3
    • USB 3.0 Device
    • 2x SATA
    • Gb Ethernet
    • QSFP+
  • Board configuration and FPGA programming
    • Aldec’s Board Configuration Controller loaded in Spartan-6 FPGA
    • Programming from Host
      • via USB 2.0 (Aldec Hes.Asic.Proto application)
      • via JTAG (Xilinx utilities)
    • Programming from Micro-SD card

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