HES7XV4000BP/HES7XV1380BP Prototyping and Emulation Main Board

Product Description

Capacity

HES7XV4000BP and HES7XV1380BP are dual Virtex-7 FPGA prototyping and emulation boards for small-medium size ASIC designs or large FPGA designs. The board is available in two configurations with XC7V2000T or XC7V690T logic modules. The estimated capacity of the largest configuration is 24 Million ASIC gates and is easily extendable via backplane non-proprietary connector (BPX). Larger capacity of 96 Million gates can be achieved with four HES7XV4000BP boards connected in the backplane board HES7BPX4. There is one SO-DIMM slot for DDR3 memory connected to one of the Virtex-7 FPGA providing up to 8GB of external RAM to the emulated design. The highest quality PCB design with proper on-board traces routing assure reliable LVDS and GTX transfers up to the device inherent limits.

Clocking

Very precisely designed clocking block provides 5 length aligned global clock lines routed to each FPGA device. It also provides multiple configuration options due to integrating different oscillators, programmable clock synthesizers and crosspoint switch multiplexers. The global clock network can be also driven from external sources via dedicated MMCX connectors as well as from backplane. The global clock network is based on LVDS signalling to assure high level of signals integrity and immunity to distractions. Complementary to global clocks there are separate clock oscillators dedicated to GTX links and DDR memories.

Hosting & Interfaces

The board configuration and monitoring controller is preloaded in a dedicated FPGA (Spartan-6) and provides USB based interface that is used by Hes.Asic.Proto board configuration and management software available on Linux and Windows host PC. Additional Kintex-7 FPGA can be used as a host bridge with PCIe x8 interface and ready to use controller preloaded by factory. The corresponding HES PCIe driver is included in Hes.Asic.Proto software package. Usage of this host controller is facilitated due to Proto-AXI interface module IP that is based on AMBA AXI standard and accompanying high abstraction level C++ API. The board has a compact form factor, standard PCIe edge connector and standard PCIe 6-pin power supply connector so it can be attached directly to the main board of a PC Host computer. Additional PCIe cable interface allows using the board stand-alone on the bench in a Lab.

Besides physical prototyping this board can be reused for HES emulation applications like simulation acceleration or co-emulation with virtual models.

BLOCK DIAGRAM

Essential Features

FPGA & Capacity

  • Main FPGA: 2 Virtex-7 XC7V2000T (FFG1761 - 850 I/O, 36 GTX)
    • ASIC Gates estimated for 60% of FPGA utilization
      • 24 Million Gates single board
      • 96 Million Gates with four boards in a backplane
  • Host FPGA: Kintex-7 XC7K325T (FBG900)
  • Debug FPGA: Spartan-6 XC6SLX150 (FFG484)

Flexible Clocking

  • Flexible global clock network connected to Virtex-7 and Kintex-7 FPGAs
    • 5 global, low-skew, length aligned clock lines with fanout buffers
    • Configurable with PLLs & Crosspoint switch muxes.
      • Precision any-frequency clock synthesizer (Si5326)
    • On-board LVDS clock sources
      • Oscillators: 192, 250, 300, 400, 500 MHz
    • External clock sources
      • 5 clocks from pair of MMCX connectors
      • 5 clocks from backplane connector
  • 1 global reference clock connected to all FPGAs (fixed at 200 MHz)
  • 2 reference clocks dedicated to GTX transceivers
    • PLL with base oscillator 250 MHz
    • Fixed oscillator 156.25 MHz
  • Separate reference oscillators for each DDR (fixed at 200MHz)
  • 60 DIFF clock lines on backplane connector

Connectivity & Expandability

  • Full size BPX backplane connector
    • High speed (25 Gbps) connectors: MOLEX 76150 series
    • Backplane to Virtex-7 aggregated connections
      • 720 I/O (360 DIFF) - standard GPIO optimized for LVDS & TDM
      • 44 GTX - high speed serial I/O
  • Inter-FPGA connections
    • Main FPGA interconnections
      • 226 I/O (113 DIFF) - standard GPIO optimized for LVDS & TDM
      • 8 GTX - high speed serial I/O
    • Main to Host FPGA connections
      • 100 I/O (46 DIFF) - standard GPIO optimized for LVDS
      • 8 GTX high speed serial I/O
    • 89 I/O common/debug bus

Memory Resources

  • Up to 8 GB of DDR3 connected to Main FPGA (Virtex-7)
  • Up to 8 GB of DDR3 connected to Host FPGA (Kintex-7)
  • Board configuration memories
    • Micro-SD card slot
    • SPI Flash

Interfaces & Hosting

  • Host FPGA:
    • PCIe, x8 Gen2 Host interfaces connected to (Kintex-7)
  • Main FPGA:
    • 2x SATA
    • USB 3.0 Device
  • Board configuration and FPGA programming
    • Aldec’s Board Configuration Controller loaded in Spartan-6 FPGA
    • Programming from Host
      • via USB 2.0 (Aldec Hes.Asic.Proto application)
      • via JTAG (Xilinx utilities)
    • Programming from Micro-SD card

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