Code Coverage (Statement/Branch, Expression/Condition, Path), Toggle Coverage, Functional Coverage (OSVVM)

Category : Assertions and Coverage Tools

Code Coverage is a debugging tool that aids the verification process. Active-HDL allows verifying source code with the following Code Coverage tools:

Statement/Branch Coverage: Statement Coverage shows execution branches for each HDL statement (this information provides feedback on which parts of the design were verified and which are untested, and also helps to locate dead code). Branch Coverage collects execution branches for if and case constructs as well as VHDL selected and conditional signal assignment statements.

Expression/Condition Coverage: Expression Coverage is a debugging tool that factorizes logical expressions and monitors them during simulation (an expression is fully covered when all of the expression cases are exercised). Condition Coverage data is a subset of statistics produced by Expression Coverage (includes only expressions used in VHDL conditional statements such as if, while, or the conditional signal assignment statement).

Path Coverage: Path Coverage is a debugging tool that collects information about the execution of program paths and analyzes whether all possible sequences of program execution were verified by a testbench (currently available for VHDL only).

The Code Coverage Viewer is a standalone application for displaying Statement Coverage, Branch Coverage, Functional Coverage, and Expression/Condition Coverage data gathered during simulation.

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